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| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 3/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Clocking and Reset
Page 100 of 144
ppb20_clock_reset.fm.01
October 15, 2001
6.3.1 Primary Interface
The primary interface is capable of operating in either the conventional PCI mode or in the PCI-X mode, at
any of the defined frequency ranges. When the IBM 133 PCI-X Bridge R2.0 is used on an add-in card, the
M66EN and PCIXCAP pins on the card edge connector should be left unconnected (except for a required
decoupling capacitor to provide an AC return path) to indicate this maximum capability. As defined by Section
9.10 of the
PCI-X Addendum to the PCI Local Bus Specification, an add-in card’sPCIXCAP pin mustbe
consistent with the 133 MHz Capable bit in the PCI-X Bridge Status register. When the bridge is used on a
motherboard, the system designer should wire the M66EN and PCIXCAP signal networks to all clients on the
bus in the architected fashion to achieve the desired results.
The bridge does not have I/O pins for the M66EN or PCIXCAP signals on its primary interface. The bridge
adjusts its internal configuration (including its internal PLL, if appropriate) solely on the basis of the initializa-
tion pattern it detects on the signals P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#. If
the internal PLL is being used (the bus is configured in the PCI-X mode), a maximum of 100
sfrom the rising
edge of P_RST# is required to lock the PLL to the frequency of the clock supplied on the P_CLK input.
6.3.2 Secondary Interface
The secondary interface is also capable of operating in either the conventional PCI mode or in the PCI-X
mode, at any of the defined frequency ranges. Since the bridge acts as the central resource for the secondary
bus, it controls the mode and frequency determination process. As recommended by Section 14.2 of the
PCI-X Addendum to the PCI Local Bus Specification, the bridge uses a programmable pull-up circuit to
accomplish this.
Figure 6-1 shows the programmable pull-up circuit and the structure of the network that is
connected to the S_PCIXCAP input of the bridge. Examples of the connections that are expected when
PCI-X 66, PCI-X 133, and conventional PCI clients are attached to the bus are also shown (see the
PCI-X
Addendum for details). There are two pull-up resistors in the circuit. The first is an external weak pull-up
whose value of 56k
is selected to set the voltage of the S_PCIXCAP input below its low threshold when a
PCI-X 66 client is attached. The second is a strong pull-up, externally wired between the S_PCIXCAP and
S_PCIXCAP_PU pins on the module. Its value of 1k
is selected to set the voltage of the S_PCIXCAP input
above its high threshold when all clients on the bus are only PCI-X 66 capable.
During the mode and frequency determination process, the S_PCIXCAP_PU driver is initially disabled, effec-
tively removing the strong pull-up resistor from the circuit. The bridge begins by sampling the value on its
S_PCIXCAP input. If it detects a b’0’ value, one or more clients have either pulled the network to ground (if
they are PCI-X 66 capable) or tied it to ground (if they are only capable of conventional PCI operation). To
distinguish between these two cases, the bridge then enables its S_PCIXCAP_PU driver to put the strong
pull-up into the circuit. If, after a sufficient time, the S_PCIXCAP input remains at a b’0’ value, the network
must be tied to ground by one or more clients, and the bus is initialized to the conventional PCI mode. If the
network can be pulled up, one or more clients are capable of only PCI-X 66 operation (and there are no
conventional PCI devices), so the bus is initialized to PCI-X 66 mode.
If the bridge initially samples a b’1’ value on the S_PCIXCAP input, then all clients on the bus are capable of
PCI-X 133 operation. The bridge then samples the S_SEL100 input to distinguish between the 66-100 MHz
and the 100-133 MHz clock frequency ranges. If it detects a b’1’ value on the S_SEL100 input, the bus is
initialized with the PCI-X 100 initialization pattern. If the value is b’0’, the PCI-X 133 initialization pattern is
used. These two ranges allow adjustment of the clock frequency to account for bus loading conditions.
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