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| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 77/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 38 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
Bridge Control
x‘3E’
Provides bridge-specific Command register extensions
Device-Specific Configuration Space Registers
Primary Data Buffering Control
x‘40’
Provides controls for primary bus memory operations
Secondary Data Buffering Control
x‘42’
Provides controls for secondary bus memory operations
Miscellaneous Control
x‘44’
Controls miscellaneous functions, such as parity error operations
Arbiter Mode
x‘50’
Controls secondary bus arbitration logic
Arbiter Enable
x‘54’
Enables arbitration for requestors of internal secondary bus arbitration logic
Arbiter Priority
x‘58’
Indicates whether high or low priority is assigned to internal secondary bus
arbitration logic requests
SERR# Disable
x‘5C’
Controls assertion of SERR# on primary bus
Primary Retry Counter
x‘60’
Defines number of primary bus retries
Secondary Retry Counter
x‘64’
Defines number of secondary bus retries
Discard Timer Control
x‘68’
Controls duration and enabling of discard timer
Retry and Timer Status
x‘6C’
Indicates expiration of a retry counter or discard timer
Opaque Memory Enable
x‘70’
Enables all opaque memory registers
Opaque Memory Base
x‘74’
Specifies base of opaque memory address range (bits 31:20)
Opaque Memory Limit
x‘76’
Specifies upper limit of opaque memory address range (bits 31:20)
Opaque Memory Base Upper 32 Bits
x‘78’
Specifies base of opaque memory address range (bits 63:32)
Opaque Memory Limit Upper 32 Bits
x‘7C’
Specifies upper limit of opaque memory address range (bits 63:32)
PCI-X ID
x‘80’
Identifies register set in Capabilities List as a PCI-X register set
Next Capabilities Pointer
x‘81’
Indicates more list items in Capabilities List
PCI-X Secondary Status
x‘82’
Reports status information about secondary interface
PCI-X Bridge Status
x‘84’
Identifies bridge capabilities and operating mode
Secondary Bus Upstream Split Trans-
action
x‘88’
Controls bridge buffers for forwarding Split Transactions from secondary
requester to primary completer
Primary Bus Downstream Split Trans-
action
x‘8C’
Controls bridge buffers for forwarding Split Transactions from primary
requester to secondary completer
Power Management ID
x‘90’
Identifies this register set in Capabilities List as a Power Management regis-
ter set.
Next Capabilities Pointer
x‘91’
Indicates that there are no more items in the Capabilities List
Power Management Capabilities
x‘92’
Reports secondary interface power management capabilities
Power Management Control/ Status
x‘94’
Reports status of secondary register
PCI-to-PCI Bridge Support Extensions
x‘96’
Indicates that clocks are not stopped on a change of power state
Data Register
x‘97’
not implemented
Secondary Bus Private Device Mask
x‘B0’
Masks devices on the secondary interface
Miscellaneous Control Register 2
x‘B8’
Provides additional control over the memory read prefetch algorithm
Table 5-1. Register Summary (Page2of 2)
Register Name
Starting
Address
Description
See
Page
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