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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 10/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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18
ICS1890
Register Access Rules
RO
-
Read Only, writes ignored
CW
-
Command OverrideWritable
RW/0
-
Read/Write only logic zero
RW
-
Read/Write
Four types of register access are supported by the device.
Read Only (RO) bits may be read, but writes are ignored.
Command OverrideWritable (CW) bits may be read, but writes
are ignored unless preceded by writing a logic one to the
Command Register Override bit (16:15). ReadWrite Zero (RW/
0) bits may be read, but must only be written with a logic zero
value. Writing a logic one to this type of bit may prevent the
device from operating normally. ReadWrite (RW) bits may be
read and may be written to any value.
Default Values
-
No default value
0
-
Default to logic zero
1
-
Default to logic one
Pin
-
Default depends on the state of the
name
named pin
Modifier
SC
-
Self Clearing
LL
-
Latching Low
LH
-
Latching High
Self clearing bits will clear without any further writes after a
specified amount of time. Latching bits are used to capture an
event. To obtain the current status of a latching bit, the bit
must be read twice in succession. If the special condition still
persists, the bit will be the same on the second read; otherwise,
the condition indication will not be present.
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PDF描述 |
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| ICS2304NZG-1LF | 2304 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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