参数资料
型号: ICS1890Y-14
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64
封装: TQFP-64
文件页数: 11/66页
文件大小: 1749K
代理商: ICS1890Y-14
19
ICS1890
Control Register (register 0 [0x00])
Control Register (register 0)
The control register is a 16-bit read/write register used to set
the basic configuration modes of the ICS1890. It is accessed
through the management interface of the MII.
Reset (bit 15)
Setting this bit to a logic 1 will reset the device and result in
the ICS1890 setting all its status and control registers to their
default values. During this process the ICS1890 may change
internal states and the states of physical links attached to it.
While in process, the bit will remain set and no other write
commands to the control register will be accepted. The reset
process will be completed within 500 ms and the bit will be
cleared indicating that the reset process is complete.
Loop Back (bit 14)
Setting this bit to a logic one causes the ICS1890 to tristate
the transmit circuitry from sending data and the receive circuitry
from receiving data. The collision detection circuitry is also
disabled unless the collision test command bit is set. Data
presented to the MII transmit data path is returned to the MII
receive data path. The delay from the assertion of Transmit
Data Enable (TXEN) to the assertion of Receive Data valid
(RXDV) will be less than 512 bit times.
Bit
Definition
When bit=0
When bit=1
Access
Default
Hex
15
Reset
no effect
reset the PHY
RW/SC
0
3
14
Loopback
disable loop back mode
enable loop back mode
RW
0
13
Data Rate
10 Mb/s operation
100 Mb/s operation
RW
1
12
Auto-Negotiation Enable
disable Auto-Negotiation
enable Auto-Negotiation
RW
1
11
Power-Down
normal mode
reduced power
consumption
RW
0
0*
10
Isolate
no effect
isolate PHY from MII
RW
0 if PHY
Address > 0
1 if PHY
Address=0
9
Restart Auto-Negotiation
no effect
restart Auto-Negotiation
RW
0
8
Duplex Mode
half duplex
full duplex
RW
0
7
Collision Test
no effect
enable collision signal test
RW
0
6
Reserved
always 0
RO
0
5
Reserved
always 0
RO
0
4
Reserved
always 0
RO
0
3
Reserved
always 0
RO
0
2
Reserved
always 0
RO
0
1
Reserved
always 0
RO
0
Reserved
always 0
RO
0
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