参数资料
型号: ICS1890Y-14
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64
封装: TQFP-64
文件页数: 37/66页
文件大小: 1749K
代理商: ICS1890Y-14
42
ICS1890
Collision Detected
10COL/(COL)
The ICS1890 asserts Collision Detected (COL) when it
detects a receive carrier (non idle condition while transmitting
(TXEN asserted).
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the un-squelched receive signal. COL is not
synchronous to either the transmit or receive clocks.
In full duplex mode, COL is disabled and always remains low.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).
Link Pulse Interface
Link Pulse Interface - Pin Mapping
When the ICS1890 is operating in the Link Pulse mode, the
MII Data Interface is remapped to accommodate the Link
PulseInterface.Thefollowingtabledetailstheexactpinmapping.
Each individual pin description also contains the new Link
Pulse Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
MII
Link Pulse
TXCLK
LTCLK
TXEN
TXER
LPTX
TXD3
TXD2
XD1
TXD0
RXCL
KLRCLK
RXDV
RXER
LPRX
RXD3
RXD2
RXD1
RXD0
CRS
COL
LSTA
SD
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
LTCLK/(TXCLK)
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the ICS1890 with a frequency of 25 MHz.
Transmit Link Pulse
LPTX/(TXER)
Data presented on this input will be transmitted as a Link Pulse
of approximately the same duration.
Receive Clock
LRCLK/(RXCLK)
The Receive Clock (LRCLK) is sourced by the ICS1890 and
is 25 MHz in frequency.
Receive Link Pulse
LPRX/(RXER)
Receive activity that is qualified as a Link Pulse will be output
on this pin as a high level of approximately the same duration
as the Link Pulse.
Signal Detect
SD/(LSTA)
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
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