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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 36/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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41
ICS1890
10M Serial Interface
10M Serial Interface - Pin Mapping
When the ICS1890 is operating in the 10M Serial mode, the
MII Data Interface is remapped to accommodate the 10M
SerialInterface.Thefollowingtabledetailstheexactpinmapping.
Each individual pin description also contains the new 10M
Serial Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
MII
10MSerial
TXCLK
10TCLK
TXEN
10TXEN
TXER
(1)
TXD3
TXD2
XD1
TXD0
10TD
RXCLK
10RCLK
RXDV
10RXDV
RXER
(1)
RXD3
RXD2
RXD1
RXD0
10RD
CRS
10CRS
COL
10COL
LSTA
(1) Error generation and detection is not supported by 10Base-
T. Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
10TCLK/(TXCLK)
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the ICS1890 to synchronize the Transmit Data
lines. In the 10M Serial Interface mode, the ICS1890 clock
frequency is 10 MHz.
Transmit Enable
10TXEN/(TXEN)
Transmit Enable (10TXEN) indicates to the ICS1890 that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion, the ICS1890
will begin reading the serial data on the transmit data line. The
ICS1890 terminates transmission of data following the de-
assertion of Transmit Enable.
Transmit Data
10TD/(TXD0)
Transmit Data 0 (10TD) is the serial transmit data bit and is
sampled continuously by the ICS1890 synchronously with
the Transmit Clock.
Receive Clock
10RCLK/(RXCLK)
The Receive Clock (10RCLK) is sourced by theICS1890 and
is 10 MHz in frequency. There are two possible sources for the
Receive Clock. When a carrier is present on the receive pair,
the source is the recovered clock from the data stream. When
no carrier is present on the receive pair, the source is the
Transmit Clock. In 10Base-T mode, the receive data pair will
be quiescent during periods of inactivity and the Transmit
Clock will be selected.
The ICS1890 will only switch between clock sources when
Receive Data Valid is de-asserted. During the period between
Carrier Sense (CRS) being asserted and Receive Data Valid
being asserted, a clock phase change of up to 360 degrees
may occur. Following the de-assertion of Receive Data valid, a
clock phase of 360 degrees may occur.
Receive Data Valid
10RXDV/(RXDV)
Receive Data Valid (10RXDV) is generated by the ICS1890.
It indicates that the ICS1890 is recovering serial data on the
Receive Data (10RD) line synchronous with the Receive Data
Clock.
The ICS1890 asserts RXDV when it detects and recovers the
preamble or the start of stream delimiter (SSD) and de-asserts
it following the last data nibble or upon detection of a signal
error. RXDV is synchronous with the Receive Data Clock
(10RCLK).
Receive Data
10RD/(RXD0)
Receive Data 0 (10RD) is the received serial data stream.
Carrier Sense
10CRS/(CRS)
The ICS1890 asserts Carrier Sense (CRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receivelinesareidleinhalfduplexmode.CRSisnotsynchronous
to either the transmit or receive clocks.
In full duplex mode and repeater mode, CRS is asserted only
on receive activity.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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