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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 35/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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40
ICS1890
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols when
it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense so collisions can not be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
STCLK/(TXCLK)
The Transmit Clock (STCLK) is a continuous clock signal
generated by the ICS1890 to synchronize the Transmit Data
lines. In the 100M Stream Interface mode, the ICS1890
clock frequency is 25 MHz.
Transmit Data 4
STD4/(TXER)
Transmit Data 4 (STD4) is the most significant bit and is
sampled continuously by the ICS1890 synchronously with
the Transmit Clock.
Transmit Data 3
STD3/(TXD3)
Transmit Data 3 (STD3) is sampled continuously by the
ICS1890 synchronously with the Transmit Clock.
Transmit Data 2
STD2/(TXD2)
Transmit Data 2 (STD2) is sampled continuously by the
ICS1890 synchronously with the Transmit Data Clock.
Transmit Data 1
STD1/(TXD1)
Transmit Data 1 (STD1) is sampled continuously by the
ICS1890 synchronously with the Transmit Clock.
Transmit Data 0
STD0/(TXD0)
Transmit Data 0 (STD0) (the least significant bit) is sampled
continuously by theICS1890 synchronously with theTransmit
Clock.
Receive Clock
SRCLK/(RXCLK)
The Receive Clock (SRCLK) is sourced by the ICS1890.
There are two possible sources for the Receive Clock (SRCLK).
When a carrier is present on the receive pair, the source is the
recovered clock from the data stream. When no carrier is
present on the receive pair, the source is the Transmit Clock
(STCLK).
The Receive Clock frequency is 25 MHz in the 100M Stream
Interface mode.
Receive Data 4
SRD4/(RXER)
Receive Error (SRD4) is the most significant bit of the receive
data nibble and is continuously asserted by the ICS1890.
Receive Data 3
SRD3/(RXD3)
Receive Data 3 (SRD3) is continuously asserted by the
ICS1890.
Receive Data 2
SRD2/(RXD2)
Receive Data 2 (SRD2) is continuously asserted by the
ICS1890.
Receive Data 1
SRD1/(RXD1)
Receive Data 1 (SRD1) is continuously asserted by the
ICS1890.
Receive Data 0
SRD0/(RXD0)
Receive Data 0 (SRD0) is the least significant bit of the receive
data nibble.
Carrier Sense
SCRS/(CRS)
Carrier Sense is provided in the 100M Stream Interface mode
as a fast receive carrier look-ahead for optional application
use. Carrier is detected using the same circuitry used in the
MII Data Interface mode that is bypassed in this mode.
The ICS1890 asserts Carrier Sense (SCRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are non-idle in half duplex mode. SCRS is not
synchronous to either the transmit or receive clocks.
In full duplex mode and repeater mode, SCRS is asserted only
on receive activity.
Signal Detect
SD/(LSTA)
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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