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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 22/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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29
ICS1890
Extended Control Register (register 16 [0x10])
Extended Control Register (register 16)
The Control Register is a 16-bit read/write register used to pre-
program the ICS1890. At power-up and reset, this register
will be loaded to the default values specified in the table
above.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to any
Command Writeable bit (CW) in any register. A write to any
register after this bit is set will reset the bit, preventing
subsequent writes to Command Write able bits from having
any effect. Therefore, each write to a Command Writeable bit
must be preceded by writing a logic one to this bit.
Bits Reserved for ICS use (14-11)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
PHY Address (Bits 10 through 6)
These five bits are used to indicate the address of the
ICS1890 on the management port of the MII (any number in
the range 0 - 31). The connection of the LEDs to the LED pins
sets the address. A read returns the address. A write is ignored.
Stream Cipher Scrambler Test Mode (Bit 5)
If set to a logic one, the scrambler will resynchronize after
252 bits of non-idle data instead of its normal time.
Bits Reserved for ICS use (Bit 4)
These bits are reserved for ICS use. These bits should only
be written as logic zero. Writing a logic one to these bits
may prevent the device from operating correctly. The
value of these bits is unspecified and may be a logic zero
or one.
NRZ/NRZ1 Encoding (bit 3)
When this bit is 1 normal NRZ1 encoding of data is performed
for 100Base-TX. When this bit is 0 NRZ coding is used
instead. NRZ encoding can be useful for system debug.
Invalid Error Code Test (bit 2)
If this bit is set to a logic one, the 4B5B encoder allows non-
data symbols to be sent when TXER is asserted. See the
Invalid Error Code Test table for the symbol mapping.
Reserved for ICS use (bit 1)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits in unspecified and may be a logic zero or one.
Stream Cipher Disable (bit 0)
If this bit is set to a logic one, the stream cipher encoder and
decoder are disabled. This will result in unscrambled IDLES
and data streams being transmitted and received for ease of
debug
Bit
Definition
When bit=0
When bit=1
Access
Default
Hex
15
Command Register Override
don’t allow writes to CW
bits
allow next write to effect
both RW & CW bits
RW
/SC
0
14
Reserved for ICS
Read unspecified
RW /0
-
13
Reserved for ICS
Read unspecified
RW /0
-
12
Reserved for ICS
Read unspecified
RW /0
-
11
Reserved for ICS
Read unspecified
RW /0
-
10
PHY address bit 4
A
RO
P4RD
9
PHY address bit 3
MII Management’s
RO
P3TD
8
PHY address bit 2
Register Address code
RO
P2LI
7
PHY address bit 1
0 - 31 Read Only
RO
P1CL
6
PHY address bit 0
Read unspecified
RO
P0AC
5
Stream Cipher Scrambler Test Mode
normal
test mode
RW
0
4
Reserved for ICS
Read unspecified
RW /0
-
3
NRZ/NRZ1 Encoding
NRZ
NRZ1
RW
1
2
Invalid Error Code Test
disabled
enabled
RW
0
1
Reserved for ICS
Read unspecified
RW /0
-
0
Stream Cipher Disable
enabled
disabled
RW
0
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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