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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 13/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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20
ICS1890
Data Rate (bit 13)
If Auto-Negotiation is disabled, setting this bit to a logic one
causes the ICS1890 to operate in the 100 Mbps mode only
and setting this bit to a logic zero causes it to operate in the 10
Mbps mode only. If Auto-Negotiation is enabled, this bit, if
read, has no meaning and, if written, has no effect on the
ICS1890operation.ThisbitalsohasnomeaningwhenHardware
Priority mode is selected with the HW/SW pin. The status of
theHW/SWpinisreflectedinregisterbit19:14.WhenHardware
Priority mode is selected, the 10/100SEL pin sets the speed.
The Data Rate status bit in the QuickPoll register (17:14)
always shows the correct setting of an active link.
Auto-Negotiation Enable (bit 12)
Setting this bit to a logic one causes theICS1890to determine
the link configuration using the auto-negotiation process.
This will be accomplished by the ICS Auto-Negotiation logic
and the state of the Data Rate (bit 13) and the Duplex Mode
(bit 8) will be ignored. Setting this bit to a logic zero will cause
the link configuration to be determined by bits 8 & 13 or the
DPXSEL & 10/100SEL pins as selected by the HW/SW pin.
This bit has no meaning when Hardware Priority mode is
selected with the HW/SW pin. In this case, the ANSEL pin
controls Auto-Negotiation use.
Power-Down (bit 11)
Setting this bit to a logic zero has no effect on the ICS1890.
Setting it to logic one will cause the ICS1890 to isolate its
transmit data output and its MII interface with the exception
of the management interface. The ICS1890 will then enter a
Low Power mode where only the management interface and
logic remain active. Setting this bit to logic zero after it has
been set to a logic one will cause the ICS1890 to power-up its
logic and then reset all error conditions. It then enables transmit
data and the MII interface.
Isolate (bit 10)
Setting this bit to a logic one causes the ICS1890 to isolate
its data paths from the MII. In this mode, sourced signals
(TXCLK, RXCLK, RXDV, RXER, RXD0-3, COL and CRS)
are in a high impedance state and input signals (TXD0-3,
TXEN and TXER) are ignored. The management interface is
unaffected by this command.
Restart Auto-Negotiation (bit 9)
Setting this bit to a logic one causes the ICS1890 to restart
auto-negotiation. Upon initiation, this bit will be reset to zero.
Setting this bit has no effect if auto-negotiation is not enabled.
Duplex Mode (bit 8)
If Auto-Negotiation is disabled, setting this bit to a logic one
causes the ICS1890 to operate in the full duplex mode and
setting this bit to a logic zero causes it to operate in the half
duplex mode. If Auto-Negotiation is enabled, this bit, if read,
has no meaning and, if written, has no effect on the ICS1890
operation. This bit also has no meaning when Hardware Priority
mode is selected with the HW/SW pin. In this case, the DPXSEL
pin sets the duplex mode. If the ICS1890 is operating in loop
back mode, this bit will have no effect on the operation.
Collision Test (bit 7)
This command bit is used to test that the collision circuitry is
working when the ICS1890 is operating in the loop back
mode. Setting this bit to a logic one causes the ICS1890 to
assert the collision signal within 512 bit times of TXEN being
asserted and to de-assert it within 4-bit times of TXEN being
de-asserted. Setting this bit to a logic zero causes theICS1890
to operate in the normal mode.
Reserved (Bits 6 through 0)
These bits are reserved for future IEEE standards. When read,
logic zeros are returned. Writing has no effect on ICS1890
operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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