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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 31/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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37
ICS1890
Pin Descriptions
MII Data Interface
The following pin descriptions apply in either 10 or 100 Mbps
mode when the MII Data Interface is selected. These pins are
re-used for the 100M Stream Interface, 10M Serial Interface,
and the Link Pulse Interface. These extra pin meanings are
described in separate interface sections with the pseudo
pin name followed by the actual pin name that the function is
mapped onto.
Transmit Clock
TXCLK
The Transmit Clock (TXCLK) is a continuous clock signal
generated by theICS1890 to synchronize information transfer
on the Transmit Enable, Transmit Data and Transmit Error
lines. The ICS1890 clock frequency is 25% of the nominal
transmit data rate. At 10 Mbps, its frequency is 2.5 MHz and at
100 Mbps is 25 MHz.
Transmit Enable
TXEN
Transmit Enable (TXEN) indicates to the ICS1890 that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion, the ICS1890
will begin reading the data nibbles on the transmit data lines. It
is the responsibility of the MAC to order the nibbles so that
the preamble is sent first, followed by destination, source,
length, data and CRC fields since theICS1890has no knowledge
of the frame structure and is merely a nibble processor. The
ICS1890 terminates transmission of nibbles following the
de-assertion of Transmit Enable (TXEN).
Transmit Data 3
TXD3
Transmit Data 3 (TXD3) is the most significant bit of the
transmit data nibble. TXD3 is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD3.
Transmit Data 2
TXD2
Transmit Data 2 (TXD2) is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD2.
Transmit Data 1
TXD1
Transmit Data 1 (TXD1) is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD1.
Transmit Data 0
TXD0
Transmit Data 0 (TXD0) is the least significant bit of the
transmit data nibble. TXD0 is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD0.
Transmit Error
TXER
When operating in the 100 Mbps mode, the assertion of
Transmit Error (TXER) for one or more clock periods will cause
the ICS1890 to emit one or more invalid symbols. The signal
must be synchronous with TXCLK. In the normal operating
mode, a HALT symbol will be substituted for the next nibble
decoded.
If the Invalid Error Code Test bit (16:2) is set, the 5-bit code
group shown in the 4B5B encoding table will be substituted
for the transmit data nibble presented.
The value of TXER during 10 Mbps operation has no effect on
the ICS1890.
Receive Clock
RXCLK
The Receive Clock (RXCLK) is sourced by the ICS1890.
There are two possible sources for the Receive Clock (RXCLK).
When a carrier is present on the receive pair, the source is the
recovered clock from the data stream. When no carrier is
present on the receive pair, the source is the Transmit Clock
(TXCLK). In 10Base-T mode, the receive data pair will be
quiescent during periods of inactivity and the Transmit Clock
will be selected. In 100Base-T mode, the IDLE symbol is sent
during periods of inactivity and the Recovered clock will be
selected.
The ICS1890 will only switch between clock sources when
Receive DataValid (RXDV) is de-asserted. During the period
between Carrier Sense (CRS) being asserted and Receive Data
Valid being asserted, a clock phase change of up to 360
degrees may occur. Following the de-assertion of Receive
Data Valid a clock phase of 360 degrees may occur.
When Receive Data Valid is asserted, the Receive Clock
frequency is 25% of the data rate, 2.5 MHz in 10Base-T mode
and 25 MHz in 100Base-T mode. The ICS1890 synchronizes
Receive Data Valid, Received Data and Receive Error with
ReceiveClock(RXCLK).
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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