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参数资料
| 型号： | ICS1890Y-14 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 34/66页 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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4
ICS1890
Interface Overviews
Overview of MAC/Repeater to PHY Interfaces
To accommodate different applications, theICS1890provides
four types of MAC/Repeater to PHY interfaces. The four
interfaces are - 10/100 MII Data Interface, 100M Stream Inter-
face, 10M Serial Interface and the Link Pulse Interface.
The standard and most commonly used interface is the 10/100
MII Data Interface which provides framed 4-bit nibbles and
control signals.
The 100M Stream Interface provides 5-bits of unframed data
as well as the normal CRS signal which can be used as a fast
look-ahead. This interface is intended for 100Base-TX repeater
applications that require nothing more than recovered parallel
data where all framing is handled in the repeater core logic.
The 10M Serial Interface provides a framed single data bit
interface with control signals and is ideally suited to applications
that already incorporate a serial 10Base-T MAC with a standard
7-wire interface.
The Link Pulse Interface is provided for applications that wish
to fully control the Auto-Negotiation process themselves but
not the actual generation and reception of Link Pulses.
MII Data Interface
The ICS1890 implements a fully compliant IEEE 802.3u
Media Independent Interface for connection to MACs or
repeaters allowing connection between the ICS1890 and
MAC on the same board, motherboard/daughter board or via
a cable in a similar manner to AUI connections.
The MII is a specification of signals and protocols which
formalizes the interfacing of a 10/100 Mbps Ethernet Media
Access Controller (MAC) to the underlying physical layer.
The specification is such that different physical media may be
supported (such as 100Base-TX, 100Base-T4 and 100Base-
FX) transparently to the MAC.
The MII Data Interface specifies transmit and receive data
paths. Each path is 4-bits wide allowing for transmission of a
data nibble. The transmit data path includes a transmit clock
for synchronous transfer, a transmit enable signal and a transmit
error signal. The receive data path includes a receive data
clock for synchronous transfer, a receive data valid signal and
a receive error signal. Both the transmit clock and receive
clock are sourced by the ICS1890.
The ICS1890 provides the MII signals carrier sense and
collision detect. In half duplex mode, carrier sense indicates
that data is being transmitted or received, and in full duplex
mode it indicates that data is being received. Collision detect
indicates that data has been received while a transmission is
in progress.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全称:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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