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参数资料
型号： LFE3-35EA-6FN484C
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
中文描述： FPGA, PBGA484
封装： 23 X 23 MM, LEAD FREE, FPBGA-484
文件页数： 2/130页
文件大小： 2667K
代理商： LFE3-35EA-6FN484C
2-7
Architecture
Lattice Semiconductor
LatticeECP3 Family Data Sheet
Figure 2-4. General Purpose PLL Diagram
Table 2-4 provides a description of the signals in the PLL blocks.
Table 2-4. PLL Blocks Signal Descriptions
Delay Locked Loops (DLL)
In addition to PLLs, the LatticeECP3 family of devices has two DLLs per device.
CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes
block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference
input of the Phase Detector (PD) input mux. The reference signal for the PD can also be generated from the Delay
Chain signals. The feedback input to the PD is generated from the CLKFB pin or from a tapped signal from the
Delay chain.
The PD produces a binary number proportional to the phase and frequency difference between the reference and
feedback signals. Based on these inputs, the ALU determines the correct digital control codes to send to the delay
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP, CLKOS, or from a user clock (pin or logic)
RST
I
“1” to reset PLL counters, VCO, charge pumps and M-dividers
RSTK
I
“1” to reset K-divider
WRDEL
I
DPA Fine Delay Adjust input
CLKOS
O
PLL output to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output to clock tree (no phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
CLKOK2
O
PLL output to clock tree (CLKOP divided by 3)
LOCK
O
“1” indicates PLL LOCK to CLKI
FDA [3:0]
I
Dynamic fine delay adjustment on CLKOS output
DRPAI[3:0]
I
Dynamic coarse phase shift, rising edge setting
DFPAI[3:0]
I
Dynamic coarse phase shift, falling edge setting
CLKFB
Divider
RST
CLKFB
CLKI
LOCK
CLKOP
CLKOS
RSTK
WRDEL
FDA[3:0]
CLKOK2
CLKOK
CLKI
Divider
PFD
VCO/
Loop Filter
CLKOP
Divider
Phase/
Duty Cycle/
Duty Trim
CLKOK
Divider
Lock
Detect
3
DRPAI[3:0]
DFPAI[3:0]
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LFE3-35EA-6FN484I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 295 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FN672C 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FN672I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FTN256C 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FTN256I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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