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| 型号： | LFE3-35EA-6FN484C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 中文描述： | FPGA, PBGA484 |
| 封装： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件页数： | 60/130页 |
| 文件大小： | 2667K |
| 代理商： | LFE3-35EA-6FN484C |
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2-32
Architecture
Lattice Semiconductor
LatticeECP3 Family Data Sheet
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-32.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as LVDS inputs.
Table 2-11. PIO Signal List
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-
tion logic.
Input Register Block
The input register blocks for the PIOs, in the left, right and top edges, contain delay elements and registers that can
be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-
faces, before they are passed to the device core. Figure 2-33 shows the input register block for the left, right and
top edges. The input register block for the bottom edge contains one element to register the input signal and no
DDR registers. The following description applies to the input register block for PIOs in the left, right and top edges
only.
Name
Type
Description
INDD
Input Data
Register bypassed input. This is not the same port as INCK.
IPA, INA, IPB, INB
Input Data
Ports to core for input data
OPOSA, ONEGA
1,
OPOSB, ONEGB
1
Output Data
Output signals from core. An exception is the ONEGB port, used for tristate logic
at the DQS pad.
CE
PIO Control
Clock enables for input and output block flip-flops.
SCLK
PIO Control
System Clock (PCLK) for input and output/TS blocks. Connected from clock ISB.
LSR
PIO Control
Local Set/Reset
ECLK1, ECLK2
PIO Control
Edge clock sources. Entire PIO selects one of two sources using mux.
ECLKDQSR
1
Read Control
From DQS_STROBE, shifted strobe for memory interfaces only.
DDRCLKPOL
1
Read Control
Ensures transfer from DQS domain to SCLK domain.
DDRLAT
1
Read Control
Used to guarantee INDDRX2 gearing by selectively enabling a D-Flip-Flop in dat-
apath.
DEL[3:0]
Read Control
Dynamic input delay control bits.
INCK
To Clock Distribution
and PLL
PIO treated as clock PIO, path to distribute to primary clocks and PLL.
TS
Tristate Data
Tristate signal from core (SDR)
DQCLK0
1, DQCLK11
Write Control
Two clocks edges, 90 degrees out of phase, used in output gearing.
DQSW
2
Write Control
Used for output and tristate logic at DQS only.
DYNDEL[7:0]
Write Control
Shifting of write clocks for specific DQS group, using 6:0 each step is approxi-
mately 25ps, 128 steps. Bit 7 is an invert (timing depends on input frequency).
There is also a static control for this 8-bit setting, enabled with a memory cell.
DCNTL[6:0]
PIO Control
Original delay code from DDR DLL
DATAVALID
1
Output Data
Status flag from DATAVALID logic, used to indicate when input data is captured in
IOLOGIC and valid to core.
READ
For DQS_Strobe
Read signal for DDR memory interface
DQSI
For DQS_Strobe
Unshifted DQS strobe from input pad
PRMBDET
For DQS_Strobe
DQSI biased to go high when DQSI is tristate, goes to input logic block as well as
core logic.
GSRN
Control from routing Global Set/Reset
1. Signals available on left/right/top edges only.
2. Selected PIO.
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| LFE3-35EA-6FN484I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 295 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FN672C | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FN672I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FTN256C | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FTN256I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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