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| 型号： | LFE3-35EA-6FN484C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 中文描述： | FPGA, PBGA484 |
| 封装： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件页数： | 78/130页 |
| 文件大小： | 2667K |
| 代理商： | LFE3-35EA-6FN484C |
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2-48
Architecture
Lattice Semiconductor
LatticeECP3 Family Data Sheet
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.
Device Configuration
All LatticeECP3 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration.
The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-
System Configuration specification. The sysCONFIG port includes seven I/Os used as dedicated pins with the
remaining pins used as dual-use pins. See TN1169, LatticeECP3 sysCONFIG Usage Guide for more information
about using the dual-use pins as general purpose I/Os.
There are various ways to configure a LatticeECP3 device:
1.
JTAG
2.
Standard Serial Peripheral Interface (SPI and SPIm modes) - interface to boot PROM memory
3.
System microprocessor to drive a x8 CPU port (PCM mode)
4.
System microprocessor to drive a serial slave SPI port (SSPI mode)
5.
Generic byte wide flash with a MachXO device, providing control and addressing
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration
port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any
time after power-up by sending the appropriate command through the TAP port.
LatticeECP3 devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device
(slave mode) with the SPI port of the FPGA to perform read-write operations.
Enhanced Configuration Options
LatticeECP3 devices have enhanced configuration features such as: decryption support, TransFR I/O and dual-
boot image support.
1.
TransFR (Transparent Field Reconfiguration)
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-
ing device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for
details.
2.
Dual-Boot Image Support
Dual-boot images are supported for applications requiring reliable remote updates of configuration data for the
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data dur-
ing download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to
the original backup golden configuration and try again. This all can be done without power cycling the system.
For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.
Soft Error Detect (SED) Support
LatticeECP3 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configura-
tion, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP3 device
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| LFE3-35EA-6FN484I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 295 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FN672C | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FN672I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FTN256C | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFE3-35EA-6FTN256I | 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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