参数资料
型号: LFE3-35EA-6FN484C
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
中文描述: FPGA, PBGA484
封装: 23 X 23 MM, LEAD FREE, FPBGA-484
文件页数: 80/130页
文件大小: 2667K
代理商: LFE3-35EA-6FN484C
www.latticesemi.com
3-1
DS1021 DC and Switching_01.7
March 2010
Preliminary Data Sheet DS1021
2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Recommended Operating Conditions
1
Absolute Maximum Ratings
1, 2, 3
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V
Input or I/O Tristate Voltage Applied
4 . . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Symbol
Parameter
Min.
Max.
Units
VCC
2
Core Supply Voltage
1.14
1.26
V
VCCAUX
2, 4
Auxiliary Supply Voltage, Terminating Resistor Switching Power
Supply (SERDES)
3.135
3.465
V
VCCPLL
PLL Supply Voltage
3.135
3.465
V
VCCIO
2, 3
I/O Driver Supply Voltage
1.14
3.465
V
VCCJ
2
Supply Voltage for IEEE 1149.1 Test Access Port
1.14
3.465
V
VREF1 and VREF2
Input Reference Voltage
0.5
1.7
V
VTT
5
Termination Voltage
0.5
1.3125
V
tJCOM
Junction Temperature, Commercial Operation
0
85
°C
tJIND
Junction Temperature, Industrial Operation
-40
100
°C
SERDES External Power Supply
6
VCCIB
Input Buffer Power Supply (1.2V)
1.14
1.26
V
Input Buffer Power Supply (1.5V)
1.425
1.575
V
VCCOB
Output Buffer Power Supply (1.2V)
1.14
1.26
V
Output Buffer Power Supply (1.5V)
1.425
1.575
V
VCCA
Transmit, Receive, PLL and Reference Clock Buffer Power Supply
1.14
1.26
V
1. For correct operation, all supplies except VREF and VTT must be held in their valid operation range. This is true independent of feature
usage.
2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-
nected to the same power supply as VCCAUX.
3. See recommended voltages by I/O standard in subsequent table.
4. VCCAUX ramp rate must not exceed 30mV/s during power-up when transitioning between 0V and 3.3V.
5. If not used, VTT should be left floating.
6. See TN1176, LatticeECP3 SERDES/PCS Usage Guide for information on board considerations for SERDES power supplies.
LatticeECP3 Family Data Sheet
DC and Switching Characteristics
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