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参数资料
型号： LFE3-35EA-6FN484C
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
中文描述： FPGA, PBGA484
封装： 23 X 23 MM, LEAD FREE, FPBGA-484
文件页数： 24/130页
文件大小： 2667K
代理商： LFE3-35EA-6FN484C
2-9
Architecture
Lattice Semiconductor
LatticeECP3 Family Data Sheet
Table 2-5. DLL Signals
LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest
EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja-
cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between
Banks 6 and 7 and Banks 2 and 3.
The outputs from the DLL and Slave Delay lines are fed to the clock distribution network.
For more information, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide.
Figure 2-6. Top-Level Block Diagram, High-Speed DLL and Slave Delay Line
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
DLL feed input from DLL output, clock net, routing or external pin
RSTN
I
Active low synchronous reset
ALUHOLD
I
Active high freezes the ALU
UDDCNTL
I
Synchronous enable signal (hold high for two cycles) from routing
CLKOP
O
The primary clock output
CLKOS
O
The secondary clock output with fine delay shift and/or division by 2 or by 4
LOCK
O
Active high phase lock indicator
INCI
I
Incremental indicator from another DLL via CIB.
GRAYI[5:0]
I
Gray-coded digital control bus from another DLL in time reference mode.
DIFF
O
Difference indicator when DCNTL is difference than the internal setting and update is needed.
INCO
O
Incremental indicator to other DLLs via CIB.
GRAYO[5:0]
O
Gray-coded digital control bus to other DLLs via CIB
CLKOP
CLKOS
LOCK
GRAY_OUT[5:0]
INC_OUT
DIFF
DCNTL[5:0]*
CLKO (to edge clock
muxes as CLKINDEL)
Slave Delay Line
LatticeECP3
High-Speed DLL
DCNTL[5:0]
CLKI
HOLD
GRAY_IN[5:0]
INC_IN
RSTN
GSRN
UDDCNTL
DCPS[5:0]
TPIO0 (L) OR TPIO1 (R)
GPLL_PIO
CIB (DATA)
CIB (CLK)
GDLL_PIO
Top ECLK1 (L) OR Top ECLK2 (R)
FB CIB (CLK)
Internal from CLKOP
GDLLFB_PIO
ECLK1
CLKFB
CLKI
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
* This signal is not user accessible. It can only be used to feed the slave delay line.
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LFE3-35EA-6FN484I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 295 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FN672C 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FN672I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 310 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FTN256C 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFE3-35EA-6FTN256I 功能描述:FPGA - 现场可编程门阵列 33.3K LUTs 133 I/O 1.2V -6 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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