参数资料
型号: LFE3-35EA-6FN484C
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
中文描述: FPGA, PBGA484
封装: 23 X 23 MM, LEAD FREE, FPBGA-484
文件页数: 91/130页
文件大小: 2667K
代理商: LFE3-35EA-6FN484C
3-11
DC and Switching Characteristics
Lattice Semiconductor
LatticeECP3 Family Data Sheet
LVPECL33
The LatticeECP3 devices support the differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard
is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL33
Table 3-3. LVPECL33 DC Conditions
1
Over Recommended Operating Conditions
Parameter
Description
Typical
Units
VCCIO
Output Driver Supply (+/-5%)
3.30
V
ZOUT
Driver Impedance
10
RS
Driver Series Resistor (+/-1%)
93
RP
Driver Parallel Resistor (+/-1%)
196
RT
Receiver Termination (+/-1%)
100
VOH
Output High Voltage
2.05
V
VOL
Output Low Voltage
1.25
V
VOD
Output Differential Voltage
0.80
V
VCM
Output Common Mode Voltage
1.65
V
ZBACK
Back Impedance
100.5
IDC
DC Output Current
12.11
mA
1. For input buffer, see LVDS table.
Transmission line,
Zo = 100 ohm differential
Off-chip
On-chip
VCCIO = 3.3V
(+/-5%)
VCCIO = 3.3V
(+/-5%)
RP = 196 ohms
(+/-1%)
RT = 100 ohms
(+/-1%)
RS = 93.1 ohms
(+/-1%)
RS = 93.1 ohms
(+/-1%)
16mA
+
-
Off-chip
On-chip
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