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参数资料
| 型号： | M58WR064KU70ZA6U |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件页数： | 44/122页 |
| 文件大小： | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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Command interface - standard commands
M58WRxxxKU, M58WRxxxKL
5.12
Block Lock command
The Block Lock command locks a block and prevents program or erase operations from
changing the data in it. All blocks are locked at power-up or reset.
Two bus write cycles are required to issue the Block Lock command.
●
The first bus cycle sets up the Block Lock command.
●
The second bus write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 17 shows the lock status after issuing a Block Lock command.
The block lock bits are volatile; once set they remain set until a hardware reset or power-
down/power-up. They are cleared by a Block Unlock command. Refer to Section 11: Block
and pseudocode for a flowchart for using the Lock command.
5.13
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or
erased. Two bus write cycles are required to issue the Block Unlock command.
●
The first bus cycle sets up the Block Unlock command.
●
The second bus write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 17 shows the protection status after issuing a Block Unlock command.
Locking operations flowchart and pseudocode for a flowchart for using the Unlock
command.
5.14
Block Lock-Down command
A locked or unlocked block can be locked-down by issuing the Block Lock-Down command.
A locked-down block cannot be programmed or erased, or have its protection status
changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and
the locked blocks can be individually unlocked by the Block Unlock command.
Two bus write cycles are required to issue the Block Lock-Down command.
●
The first bus cycle sets up the Block Lock command.
●
The second bus write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Locked-down blocks revert to the locked (and not locked-down) state when the
device is reset on power-down. Table 17 shows the lock status after issuing a Block Lock-
down command. Refer to Section 11: Block locking for a detailed explanation and Appendix
C, Figure 26: Locking operations flowchart and pseudocode for a flowchart for using the
Lock-Down command.
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| M3L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L14FCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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