参数资料
型号: M58WR064KU70ZA6U
厂商: NUMONYX
元件分类: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封装: 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件页数: 5/122页
文件大小: 2187K
代理商: M58WR064KU70ZA6U
Common flash interface
M58WRxxxKU, M58WRxxxKL
102/123
Table 46.
Bank and erase block region 2 information(1)
M58WR016KU,
M58WR032KU,
M58WR064KU
M58WR016KL,
M58WR032KL,
M58WR064KL
Description
Offset
Data
Offset
Data
(P+28)h = 61h
01h
(P+30)h = 69h
03h(2)
07h(3)
0Fh(4)
Number of identical banks within Bank Region 2
(P+29)h = 62h
00h
(P+31)h = 6Ah
00h
(P+2A)h = 63h
11h
(P+32)h = 6Bh
11h
Number of program or erase operations allowed in Bank
Region 2:
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
(P+2B)h = 64h
00h
(P+33)h = 6Ch
00h
Number of program or erase operations allowed in other
banks while a bank in this region is programming
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
(P+2C)h = 65h
00h
(P+34)h = 6Dh
00h
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
(P+2D)h = 66h
02h
(P+35)h = 6Eh
01h
Types of erase block regions in Bank Region 2
n = number of erase block regions with contiguous same-
size erase blocks.
Symmetrically blocked banks have one blocking region.(5)
(P+2E)h = 67h
06h
(P+36)h = 6Fh
07h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+2F)h = 68h
00h
(P+37)h = 70h
00h
(P+30)h = 69h
00h
(P+38)h = 71h
00h
(P+31)h = 6Ah
01h
(P+39)h = 72h
01h
(P+32)h = 6Bh
64h
(P+3A)h = 73h
64h
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+33)h = 6Ch
00h
(P+3B)h = 74h
00h
(P+34)h = 6Dh
01h
(P+3C)h = 75h
01h
Bank Region 2 (Erase Block Type 1): bits per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+35)h = 6Eh
03h
(P+3D)h = 76h
03h
Bank Region 2 (Erase Block Type 1): Page mode and
synchronous mode capabilities (defined in Table 43)
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
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