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参数资料
| 型号： | M58WR064KU70ZA6U |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件页数： | 61/122页 |
| 文件大小： | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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M58WRxxxKU, M58WRxxxKL
Configuration register
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8.4
Wait polarity bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data is valid or a
WAIT state must be inserted. The wait polarity bit sets the polarity of the Wait signal. When
the wait polarity bit is set to ‘0’ the Wait signal is active Low, and when it is set to ‘1’ the Wait
signal is active High.
8.5
Data output configuration bit (CR9)
The data output configuration bit determines whether the output remains valid for one or two
clock cycles. When the data output configuration bit is ’0’ the output data is valid for one
clock cycle, and when it is ’1’ the output data is valid for two clock cycles.
The data output configuration depends on the condition:
●
tK > tKQV + tQVK_CPU
where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU
and tKQV is the clock to data valid time. If this condition is not satisfied, the data output
configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 7: X-latency and data
8.6
Wait configuration bit (CR8)
In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is
asserted, data is not valid and when WAIT is deasserted, data is valid.
When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait
bit is ’1’ the Wait output pin is asserted one clock cycle before the wait state.
8.7
Burst type bit (CR7)
The burst type bit configures the sequence of addresses read as sequential or interleaved.
When the burst type bit is ’0’ the memory outputs from interleaved addresses, and when the
burst type bit is ’1’ the memory outputs from sequential addresses. See Table 13: Burst type
definition for the sequence of addresses output from a given starting address in each mode.
8.8
Valid clock edge bit (CR6)
The valid clock edge bit, CR6, configures the active edge of the Clock, K, during
synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of
the Clock is the active edge, and when it is ’1’ the rising edge of the Clock is active.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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