收藏本站
参数资料
型号： MRF89XAT-I/MQ
厂商： Microchip Technology
文件页数： 57/140页
文件大小： 0K
描述： RF ISM BAND TXRX 32 QFN
标准包装： 1
频率： 863MHz ~ 870MHz，902MHz ~ 928MHz，950MHz ~ 960MHz
数据传输率 - 最大： 200kbps
调制或协议： FSK，OOK
应用： ISM
功率 - 输出： 12.5dBm
灵敏度： -113dBm
电源电压： 2.1 V ~ 3.6 V
电流 - 接收： 3mA
电流 - 传输： 25mA
数据接口： PCB，表面贴装
存储容量： *
天线连接器： PCB，表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 32-WFQFN 裸露焊盘
包装： 标准包装
其它名称： MRF89XAT-I/MQDKR
MRF89XA
3.2
Frequency Synthesis Description
3.2.4.1
PLL Requirements
3.2.1
REFERENCE OSCILLATOR
With integer-N PLL architecture, the following
conditions must be met to ensure correct operation:
The crystal oscillator (XTAL) forms the reference
oscillator of an Integer-N PLL. The crystal reference
frequency and the software controlled dividers R, P,
and S determine the output frequency of the PLL. The
guidelines for selecting the appropriate crystal with
specifications are explained in Section 4.6, Crystal
Specification and Selection Guidelines .
Note: Use the recommended values provided in
the Bill Of Materials (BOM) in Section 4.7,
Bill of Materials for any PLL prototype
design.
3.2.2 BUFFERED CLOCK OUTPUT
The buffered clock output is a signal derived from f xtal .
It can be used as a reference clock (or a sub-multiple
of it) for the host microcontroller and is an output on the
? The comparison frequency, F COMP , of the Phase
Frequency Detector (PFD) input must remain
higher than six times the PLL bandwidth (PLLBW)
to guarantee loop stability and to reject harmonics
of the comparison frequency F COMP . This is
expressed in the inequality:
F COMP ≥ 6 * PLLBW
? However the PLLBW must be sufficiently high to
allow adequate PLL lock times.
? Because the divider ratio R determines F COMP , it
should be set close to 119, leading to
F COMP ≈ 100 kHz, which will ensure suitable PLL
stability and speed.
The following criteria govern the R, P, and S values for
the PLL block:
CLKOUT pin (pin 19). The pin is activated using the
CLKOCNTRL bit (CLKOUTREG<7>). The output
frequency (CLKOUT) division ratio is programmed
through the Clock Out Frequency bits (CLKOFREQ5-
CLK0FREQ1) in the Clock Output Control Register
(CLKOUTREG<6:2>). The two uses of the CLKOUT
?
?
?
?
64 ≤ R ≤ 169
P+1 > S
PLLBW = 15 kHz nominal
Start-up times and reference frequency drives as
specified
output are:
3.2.4.2
PLL Lock Detection Indicator
? To provide a clock output for a host microcontroller,
thus saving the cost of an additional oscillator.
CLKOUT can be made available in any operation
mode, except Sleep mode, and is automatically
enabled at power-up.
? To provide an oscillator reference output.
Measurement of the CLKOUT signal enables
simple software trimming of the initial crystal
tolerance.
The MRF89XA features a PLL lock detect indicator.
This is useful for optimizing power consumption, by
adjusting the frequency synthesizer wake-up time
(TSFS). For more information on TSFS, refer
Table 5-4 . The lock status is available by reading the
Lock Status of PLL bit (LSTSPLL) in the FIFO
Transmit PLL and RSSI Interrupt Request
Configuration register (FTPRIREG<1>), and must be
cleared by writing a ‘ 1 ’ to this same register. The
Note:
CLKOUT is disabled when the MRF89XA
is in Sleep mode. If Sleep mode is used,
the host microcontroller must have provi-
lock status can also be seen on the PLOCK pin (pin
23) of the device, by setting the LENPLL bit
(FTPRIREG<0>).
sions to run from its own clock source.
Note:
The LSTSPLL bit latches high each time
3.2.3
CLOCK REGISTERS
the PLL locks and must be reset by writing
a ‘ 1 ’ to LSTSPLL from FTPRIREG.
The registers associated with the Clock and its control
are:
3.2.5
PLL REGISTERS
? GCONREG ( Register 2-1 )
? CLKOUTREG ( Register 2-28 ).
The registers associated with the PLL are:
? GCONREG ( Register 2-1 )
3.2.4
PHASE-LOCKED LOOP (PLL)
? FTPRIREG ( Register 2-15 ).
The frequency synthesizer of the MRF89XA is a fully
3.2.6
SW SETTINGS OF THE VCO
integrated integer-N type PLL. The PLL circuit requires
only five external components for the PLL loop filter
and the VCO tank circuit.
To guarantee the optimum operation of the VCO over
the MRF89XA’s frequency and temperature ranges,
the settings listed in Table 3-1 should be programmed
into the MRF89XA.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 57
相关PDF资料
PDF描述
241-5-12L XFRMR PWR 115V 12.6VCT 1A LEADS
DPC-40-250 XFRMR PWR 115/230V 40VCT 250MA
ST-5-56 XFRMR PWR 115V 28V 440MA 12VA
6221 TIP STAIN-STEEL SHARP-PT .06"DMM
ST-5-48 XFRMR PWR 115V 24V 500MA 12VA
相关代理商/技术参数
参数描述
MRF8HP21080HR3 功能描述:射频MOSFET电源晶体管 HV8 2.1GHZ 160W NI780H-4 RoHS:否 制造商:Freescale Semiconductor 配置:Single 晶体管极性: 频率:1800 MHz to 2000 MHz 增益:27 dB 输出功率:100 W 汲极/源极击穿电压: 漏极连续电流: 闸/源击穿电压: 最大工作温度: 封装 / 箱体:NI-780-4 封装:Tray
MRF8HP21080HR5 功能描述:射频MOSFET电源晶体管 HV8 2.1GHZ 160W NI780H-4 RoHS:否 制造商:Freescale Semiconductor 配置:Single 晶体管极性: 频率:1800 MHz to 2000 MHz 增益:27 dB 输出功率:100 W 汲极/源极击穿电压: 漏极连续电流: 闸/源击穿电压: 最大工作温度: 封装 / 箱体:NI-780-4 封装:Tray
MRF8HP21080HSR3 功能描述:射频MOSFET电源晶体管 HV8 2.1GHZ 160W NI780S-4 RoHS:否 制造商:Freescale Semiconductor 配置:Single 晶体管极性: 频率:1800 MHz to 2000 MHz 增益:27 dB 输出功率:100 W 汲极/源极击穿电压: 漏极连续电流: 闸/源击穿电压: 最大工作温度: 封装 / 箱体:NI-780-4 封装:Tray
MRF8HP21080HSR5 功能描述:射频MOSFET电源晶体管 HV8 2.1GHZ 160W NI780S-4 RoHS:否 制造商:Freescale Semiconductor 配置:Single 晶体管极性: 频率:1800 MHz to 2000 MHz 增益:27 dB 输出功率:100 W 汲极/源极击穿电压: 漏极连续电流: 闸/源击穿电压: 最大工作温度: 封装 / 箱体:NI-780-4 封装:Tray
MRF8HP21130HR3 功能描述:射频MOSFET电源晶体管 HV8 2.1GHZ 130W NI780-4 RoHS:否 制造商:Freescale Semiconductor 配置:Single 晶体管极性: 频率:1800 MHz to 2000 MHz 增益:27 dB 输出功率:100 W 汲极/源极击穿电压: 漏极连续电流: 闸/源击穿电压: 最大工作温度: 封装 / 箱体:NI-780-4 封装:Tray
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*