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| 型号： | MT46V32M8BG-6AT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件页数： | 10/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
18
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – IDD
Table 7:
IDD Specifications and Conditions (x16: -5B, -6, -6T, -75E, -75Z, -75) - Die Revision G Only
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V (-5B); VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (-6, -6T, -75E, -7Z, -75);
0°C
≤ T
Parameter/Condition
Symbol
-5B
-6/6T -75E -75Z
-75
Units
Notes
Operating one-bank precharge current: tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every
two clock cycles
IDD0
135
125
120
mA
Operating one-bank active-read-precharge current:
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =0mA;
Address and control inputs changing once per clock cycle
IDD1
185
180
170
155
mA
Precharge power-down standby current: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD2P
44444
mA
Idle standby current: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle; VIN =VREF for DQ, DQS,
and DM
IDD2F
60
50
45
mA
Active power-down standby current: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
40
30
25
30
mA
Active standby current: CS# = HIGH; CKE = HIGH; One bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD3N
70
60
50
mA
Operating burst read current: Burst = 2; Continuous
burst reads; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN);
IOUT =0mA
IDD4R
260
220
185
mA
Operating burst write current: Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
IDD4W
215
195
160
mA
Auto refresh burst current:
tREFC = tRFC (MIN)
IDD5
260
255
235
245
mA
tREFC = 7.8s
IDD5A
66666
mA
Self refresh current: CKE
≤ 0.2V
Standard
IDD6
44444
mA
Low power (L)
IDD6A
22222
mA
Operating bank interleave read current: Four-bank
interleaving READs (burst = 4) with auto precharge;
tRC = minimum tRC allowed; tCK = tCK (MIN); Address and
control inputs change only during ACTIVE, READ, or WRITE
commands
IDD7
510
440
380
400
mA
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