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| 型号： | MT46V32M8BG-6AT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件页数： | 4/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
12
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Pin and Ball Assignments and Descriptions
Table 4:
Pin and Ball Descriptions
FBGA
Numbers
TSOP
Numbers
Symbol
Type
Description
K7, L8, L7,
M8, M2, L3,
L2, K3, K2,
J3, K8,
J2, H2
29, 30, 31,
32, 35, 36,
37, 38, 39,
40, 28
41, 42
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10,
A11, A12
Input
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
J8, J7
26, 27
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0 and BA1 also define which mode register (mode register or
extended mode register) is loaded during the LOAD MODE
REGISTER (LMR) command.
G2, G3
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
H3
44
CKE
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers, and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle) or ACTIVE POWER-DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER-DOWN entry and exit and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH throughout
read and write accesses. Input buffers (excluding CK, CK#, and CKE)
are disabled during POWER- DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but will
detect an LVCMOS
LOW level after VDD is applied and until CKE is
first brought HIGH, after which it becomes a SSTL_2 input only.
H8
24
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple banks. CS# is considered part of the command
code.
F3
F7, F3
47
20, 47
DM
LDM, UDM
Input
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. For the x16, LDM is DM for DQ0–
DQ7 and UDM is DM for DQ8–DQ15. Pin 20 is a NC on x4 and x8.
H7, G8, G7
23, 22, 21
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
A8, B9, B7,
C9, C7, D9,
D7, E9, E1,
D3, D1, C3,
C1, B3, B1,
A2
2, 4, 5,
7, 8, 10,
11, 13, 54,
56, 57, 59,
60, 62, 63,
65
DQ0–DQ2
DQ3–DQ5
DQ6–DQ8
DQ9–DQ11
DQ12–DQ14
DQ15
I/O
Data input/output: Data bus for x16.
A8, B7, C7,
D7, D3, C3,
B3, A2
2, 5, 8,
11, 56, 59,
62, 65
DQ0–DQ2
DQ3–DQ5
DQ6, DQ7
I/O
Data input/output: Data bus for x8.
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