参数资料
型号: MT46V32M8BG-6AT:G
元件分类: DRAM
英文描述: 32M X 8 DDR DRAM, 0.7 ns, PBGA60
封装: (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60
文件页数: 55/93页
文件大小: 3632K
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
57
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 24. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 35 on page 58 indi-
cates the operating frequencies at which each CL setting can be used.
Figure 24:
CAS Latency
Note:
BL = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
Command
DQ
DQS
CL = 2
READ
NOP
READ
NOP
CK
CK#
Command
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
Don’t Care
Transitioning Data
READ
NOP
CK
CK#
Command
DQ
DQS
CL = 3
T0
T1
T2
T3
T3n
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