PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
9
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Functional Block Diagrams
Figure 4:
32 Meg x 8 Functional Block Diagram
Figure 5:
16 Meg x 16 Functional Block Diagram
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
10
COMMAND
DECODE
A0–A12,
BA0, BA1
CKE
13
ADDRESS
REGISTER
15
512
(x16)
8192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8192 x 512 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
15
BANK1
BANK2
BANK3
13
9
2
REFRESH
COUNTER
8
1
INPUT
REGISTERS
1
RCVRS
1
16
2
16
CK
Out
DATA
DQS
MASK
DATA
CK
In
DRVRS
DLL
MUX
DQS
GENERATOR
8
16
DQ0–DQ7
DQS
1
READ
LATCH
WRITE
FIFO
&
DRIVERS
1
COL0
DM
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
9
COMMAND
DECODE
A0–A12,
BA0, BA1
CKE
13
ADDRESS
REGISTER
15
256
(x32)
8192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
15
BANK1
BANK2
BANK3
13
8
2
REFRESH
COUNTER
16
2
INPUT
REGISTERS
2
RCVRS
2
32
4
32
CK
Out
DATA
DQS
MASK
DATA
CK
In
DRVRS
DLL
MUX
DQS
GENERATOR
16
32
DQ0–DQ15
LDQS
UDQS
2
READ
LATCH
WRITE
FIFO
&
DRIVERS
1
COL0
LDM,
UDM