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| 型号： | MT46V32M8BG-6AT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件页数： | 72/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
72
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 37:
Data Output Timing – tAC and tDQSCK
Notes:
1. READ command with CL = 2 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the “long term” component of the
DQS skew.
3. DQ transitioning after DQS transition define the tDQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
WRITE
During a WRITE command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst (after tWR time); if auto precharge is not
selected, the row will remain open for subsequent accesses.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
Note:
For the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle).
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(that is, tDQSS [MIN] and tDQSS [MAX]) might not be intuitive; they have also been
= 4. Upon completion of a burst, assuming no other commands have been initiated, the
DQ will remain High-Z and any additional input data will be ignored.
CK
CK#
DQS or LDQS/UDQS3
T1
T2
T3
T4
T5
T2n
T3n
T4n
T5n
T6
tRPST
tLZ (MIN)
tDQSCK2 (MAX)
tDQSCK2 (MIN)
tDQSCK2 (MAX)
tDQSCK2 (MIN)
tHZ (MAX)
All DQ values collectively4
tAC5 (MIN)
tAC5 (MAX)
tLZ (MIN)
tHZ (MAX)
T2
T2n
T3n
T4n
T5n
T2n
T3n
T4n
T5n
T3
T4
T5
T2
T3
T4
T5
T3
DQ (last data valid)
DQ (first data valid)
T01
tRPRE
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