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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 1/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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orli10g_01
ORCA ORLI10G
Quad 2.5Gbps, 10Gbps
Quad 3.125Gbps, 12.5Gbps Line Interface FPSC
September 2002
Data Sheet
Introduction
Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a exi-
ble FPGA logic core. Built on the Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the
ORLI10G consists of an OIF standard compliant (OIF-SFI4-01.0) SFI-4.1 or IEEE
802.3ae compliant XSBI, 10
Gbits/s or 12.5 Gbits/s transmit and 10 Gbits/s or 12.5 Gbits/s receive line interface.
Both transmit and receive interfaces consist of 16-bit LVDS data at up to 850 Mbits/s, integrated transmit and
receive programmable PLLs for data rate conversions between the line-side and system-side data rates, and a pro-
grammable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with
strong FEC system device data standards. In addition to the embedded functionality, the device includes over 400k
of usable FPGA gates. The line interface includes logic to divide the data rate down to 212 MHz or less (1/4 line
rate) or 106 MHz or less (1/8 line rate) for transfer to the FPGA logic. The ORLI10G is designed to connect to a
plethora of industry standard devices on the line side. The programmable logic interface on the system side allows
direct connection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH framer/data engine, or a 10 Gbits/s/12.5
Gbits/s digital wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the Physical Coding Sublayer (PCS), interfaces to the Physical
Media Attachment (PMA), and connects to the system interface (host or switch) for the proposed IEEE 802.3ae 10
Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable device for 10 Gbits/s data solutions. It can be used as the
interface between the line interface and the system interface in a variety of emerging networks, including 10 Gbits/s
SONET/SDH (OC-192/STM-48), 10 Gbits/s Optical Transport Networks (OTN) using digital wrapper and strong
FEC, or 10 Gbits/s Ethernet. Other functions include use in quad OC-48/ STM-16 SONET/SDH systems, interfaces
between quad OC-48/STM-16 and OC-192/STM-64 components, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is received at the line interface and then sent to either a 4-bit or 8-bit
serial-to-parallel converter. On the transmit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. Thus,
the data rate at the internal FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for great exibility in handling clock rate conversion due to differ-
ing amounts of overhead bits in various system data standards. For example, the ORLI10G can divide down the
STS-192/STM-64 SONET/SDH data line rate of 622 MHz by 4 to synchronize with a 155 MHz system clock, or the
12.5 Gbits/s Super-FEC data line rate of 781 MHz can be divided by 8 MHz to 98 MHz system clock or by 8 x 4/5 to
provide a 78 MHz system data rate.
Table 1. ORCA ORLI10G–Available FPGA Logic (equivalent to ORCA OR4E04)
* 316 are available in the 680 PBGAM package.
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with
40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 6 PLLs.
Device
PFU
Rows
PFU
Columns
Total
PFUs
FPGA
Max. User
I/Os*
LUTs
EBR
Blocks
EBR Bits
(k)
FPGA
System
Gates (k)
ORLI10G
36
1,296
316
10,368
12
111
333—643
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PDF描述 |
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| ORLI10G2BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORLI10G3BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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