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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 5/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
13
Receive Path Details
In the receive path, the ORLI10G embedded core can be broken down into three sections: the high-speed line
interface, the demultiplexer, and the receive-side onboard PLLs. Note that both transmit and receive PLLs are in
addition to the four Programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
Line Interface
In the receive path, 16-bit data and associated clocks are inputs to the line interface. Typical data rates are
expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS input data bus is actually
composed of four 4-bit data buses with one clock for each 4-bit data bus. In the 10G mode, all four input clocks are
tied together internal to the device and driven by the lowest-order input clock. In 2.5G mode, the four clocks may be
asynchronous to each other. The ORLI10G uses LVDS (Low-Voltage Differential Signaling) drivers/receivers, which
are intended to provide point-to-point connection between the ORLI10G and optical transceiver (MUX/deMUX)
parts. The LVDS inputs are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS
inputs are terminated with a 100 resistor to improve performance.
The receive line interface on the ORLI10G can connect to devices that are compliant to either the XSBI standard or
the SFI-4 standard. The major difference for these standards is that for XSBI (IEEE 802.3ae version 2.1), the least
signicant bit [0] is received rst after deserialization by the external deMUX device, whereas SFI-4 receives the
most signicant bit rst. In some cases, bits [15:0] on the ORLI10G should be connected to bits [0:15] on the
device to which the ORLI10G device interfaces. An example of this is the PCS IP core in the ORLI10G when the
ORLI10G is connected to an XSBI version 2.1 device.
It should be noted that IEEE 802.3ae version 3.1 to D3.4 (version D3.4 is the latest draft version of this specica-
tion as of the writing of this data sheet) swaps XSBI so that the most signicant bit is received rst, thus requiring
that bits [0:15] on the ORLI10G be connected directly to bits [0:15] on the XSBI device.
DeMUX
The demultiplexer takes the high-speed line data and clocks and converts the data and clock to rates appropriate
for transfer to the FPGA logic. The demultiplexer supports two modes of operation:
Divide-by-8
– 10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to 850
Mbits/s into 128 bits at 78 Mbits/s to 106 Mbits/s. The incoming clocks are divided by 8.
– 2.5G (or quad channel): The demultiplexer converts the incoming four bits of data at 622 Mbits/s to 850
Mbits/s into 32 bits at 78 Mbits/s to 106 Mbits/s. The associated clock is also divided by 8. This is repeated
four times with each 4-bit data/clock group assumed to be asynchronous to the others.
Divide-by-4
– 10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to
850 Mbits/s into 64 bits at 156 Mbits/s to 212 Mbits/s. The incoming clocks are divided by 4.
– 2.5G (or quad channel): The demultiplexer converts the incoming 4 bits of data at 622 Mbits/s to 850 Mbits/s
into 16 bits at 156 Mbits/s to 212 Mbits/s. The associated clock is also divided by 4. This is repeated four
times with each 4-bit data/clock group assumed to be asynchronous to the others.
Onboard Receive PLLs
The function of the onboard PLLs is to align the system data with the line data, which will be at a slightly higher rate
owing to the addition of the overhead bits. There are two PLLs on the receive path. The input to the rst PLL,
RX1_PLL (see Figure 3), is the divided down lowest-order clock from the demultiplexer. The RX1_PLL generates a
clock with a user-dened frequency ratio of M/N to the divided clock. This clock would generally be used to com-
pensate for different data rates due to overhead bits. M and N can independently be set from 1 to 40.
The RX2_PLL also takes its input from the divided down clock and is used to provide a balanced, divided clock
across the FPGA-embedded core interface.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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