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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 23/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
3
New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL. Programmable (on/off) internal parallel termination (100 )
also supported for these I/Os.
New capability to (de)multiplex I/O signals:
–New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
–New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, organized to allow two nibbles to act independently,
plus one extra for arithmetic operations.
–New register control in each PFU has two independent programmable clocks, clock enables, local set/reset,
and data selects.
–New LUT structure allows exible combinations of LUT4, LUT5, new LUT6, 4 : 1 MUX, new 8 : 1 MUX, and
ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, congurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing, which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
–Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efcient performance.
SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PAL-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell.
New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be congured as:
– 1—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1k x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
–2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
–Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-
in system registers that act as the control and status center for the device.
Built-in testability:
– Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only.
– Programming and readback through boundary-scan port compliant to IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
–New temperature-sensing diode.
Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provides optimum clock
modication and conditioning for phase, frequency, and duty cycle from 20 MHz up to
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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