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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 2/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
10
ORLI10G Overview
Device Layout
The ORLI10G FPSC provides a high-speed transmit and receive line interface combined with FPGA logic. The
device is based on the 1.5 V OR4E04 FPGA. The ORLI10G consists of an embedded backplane transceiver core
and a full OR4E04 36x36 FPGA array.
The ORLI10G is a line interface device that contains an FPGA base array, a 10 Gbits/s line interface block, and
programmable PLLs to do the overhead clock rate conversions on a single monolithic chip. The embedded portion
includes:
Line Interface: This consists of a 16-bit LVDS receive data bus and a 16-bit LVDS transmit bus operating up to
850 Mbits/s per input/output pair. Each 4-bit LVDS I/O has a high-speed LVDS clock (operating up to 850 MHz)
associated with it. The bit order (i.e. whether bit 0 is the most signicant or least signicant bit) of the 16-bit trans-
mitted and received busses can be dened separately in the user's programmable logic netlist that interfaces to
the embedded core so that any required interface standard can be met.
MUX/deMUX: This performs the MUXing and deMUXing between the high-speed line interface data operating at
the line rate and system data operating at 1/4 or 1/8 the line rate.
On-board PLLs: This is used to align system-side data with the line-side data, which is at a slightly higher data
bandwidth than the system data because of the addition of overhead due to encoding.
Figure 2 shows the ORLI10G block diagram.
10G Mode
The ORLI10G can operate in one of two data modes: 10G mode or Quad 2.5G mode.
In 10G (or single-channel) mode, all 16 LVDS transmit data outputs are assumed to be one data bus with one
LVDS clock provided off chip for the data. Likewise, all 16 LVDS receive data inputs are assumed to be one data
bus with one LVDS input clock provided for the data.
Transmit Path
In 10G mode, the transmit data from the FPGA logic is passed to the embedded core as a single 128- or 64-bit bus.
An off-chip transmit reference clock is divided down in the core by 8 (for 128-bit to 16-bit MUX) or by 4 (for 64-bit to
16-bit MUX). All four transmit clock outputs are therefore synchronized.
Receive Path
The 16-bit receive data is deMUXed in the embedded core to a single 128-bit or 64-bit data bus and passed to the
FPGA logic. The lowest-order LVDS input clock (rx_clk_in[0]) is used as the receive clock for all 16 data bits (the
other three LVDS input clock pairs should be left unconnected). This clock is divided down in the core by 8 (for 16-
bit to 128-bit deMUX) or by 4 (for 16-bit to 64-bit deMUX) and passed to the FPGA logic with the data.
The ORLI10G supports transmit and receive data rates up to 850 Mbits/s. Therefore, the total data rate for this
mode is 850 Mbits/s x 16 or 13.6 Gbits/s.
2.5G Mode
In 2.5G (or quad-channel) mode, the 16 LVDS receive data inputs are assumed to be four independent 4-bit data
buses with four LVDS asynchronous input clocks provided for each data bus. There is no 2.5 G mode in the trans-
mit direction for the ORLI10G device.
Receive Path
Each of the four 4-bit receive data buses are deMUXed in the embedded core to one of four independent 32- or 16-
bit data buses and passed to the FPGA logic. The four receive clock inputs are divided down in the core by 8 (for
each 4- to 32-bit deMUX) or by 4 (for each
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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