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参数资料
| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 9/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
17
ORLI10G Demultiplexer (Rx) Detail
The demultiplexer module converts the incoming 16 bits of data at 622 MHz/850 MHz into 128 bits of data at 78
MHz/106 MHz or 64 bits of data at 156 MHz/212 MHz and sends it to the FPGA logic. It has been implemented in
two stages; the rst stage converts each incoming bit into a byte stream and the second stage bit interleaves these
bytes into 128/64 bits, depending upon the mode of operation. The low-speed clocks are generated by this block.
These clocks are then driven back to this block from the low-speed clock tree network. Functionally, the demulti-
plexer architecture consists of three blocks: the serial to parallel conversion, the counters, and the interleaving.
The rst stage of the line interface module (demultiplexer) converts each incoming bit of data into a byte stream on
a divided-by-8 clock. The data is rst registered on the rising edge of the clock input. The clock dividers also runs
parallel to data shift (serial to parallel) on the rising edge of the input clock. An enable is created when a complete
byte is taken in. This enable signal is used to register the serial-to-parallel converted data at the high-speed input
clock. This ensures that the data can be safely transferred to the low-speed clock. This data is then transferred to
the divided clock, allowing a timing margin of approximately half the divided clock period.
The high-speed demultiplexer converts the incoming data as blocks of bytes. The byte boundaries of incoming data
are unknown and are irrelevant to this module.
This data is then interleaved to the 128/64 bits of output data, depending on the mode of operation (divide-by-
4/divide-by-8). In 10G mode, the output data is assigned the retimed 128/64 bits of data from the rst stage of line
interface registered at the input clock [0]. In 2.5G mode, the output data is assigned four concatenated 32/16 bits of
data from the rst stage of line interface registered at input clocks [0 to 3]. The interleaving is done at bit level
because the serial-to-parallel converter operates on bits of incoming data. In 10G mode, it is assumed that all the
incoming 16 bits of data are synchronized to the input clock [0]. This block also generates the clock enables used
by the output line interface (multiplexer) module for registering the data on the high-speed clock. These enables
along with the enables from other clocks are selected through the high-speed clock MUX for the output line inter-
face block.
Figure 6 shows the valid data output bits from the demultiplexer in each of the four modes (divide-by-8, 10G and
2.5G modes, and divide-by-4, 10G and 2.5G modes). Figure 7—Figure 10 show the demultiplexer input data and
clock waveforms and output clock, enable, and data waveforms for all four modes.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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