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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 34/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
4
420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x is possible.
New cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route.
This feature also supports compliance with many setup/hold and clock-to-out I/O specications, and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
Programmable Logic System Features
PCI local bus compliant for FPGA I/Os.
Improved PowerPC
/PowerQUICC 860, and PowerPC/PowerQUICC II MPC8260 high-speed synchronous
microprocessor interface can be used for conguration, readback, device control, and device status, as well as
for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface
to synchronous PowerPC processors with user-congurable address space is provided.
New embedded AMBA specication 2.0 AHB system bus (ARM
processor) facilitates communication among
the microprocessor interface, conguration logic, embedded block RAM, FPGA logic, and embedded standard
cell blocks.
Variable-size bused readback of conguration data capability with the built-in microprocessor interface and sys-
tem bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew (<200
ps for OR4E04).
New local clock routing structures allow creation of localized clock trees.
Two new edge clock structures allow up to six highspeed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-
speed memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced-speed internal
logic.
ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis,
simulation, and timing analysis.
Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-PHY3.
Also meets proposed specications for UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces.
Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-over-SONET as
dened by the Saturn Group.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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