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| 型号： | ORLI10G1BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 25/78页 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
31
Typically, the following reset sequence should be followed for the ORLI10G:
Place the device in reset by driving RESET_TX = 1 and RESET_RX = 1 (or FPGA_RESET signal = 1), and by
placing the FPGA portion into reset.
Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0 and FPGA_RESET
signal = 0).
Release the FPGA portion from reset.
Line Interface Circuit Specications
Power Supply Decoupling LC Circuit
The 622 MHz—850 MHz line interface macro contains both analog and digital circuitry. The line interface function,
for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop
to provide its divided clocks. The internal analog phase-locked loop contains a voltage-controlled oscillator. This cir-
cuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the band-
width of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit ele-
ments.
Additional power supply ltering in the form of an LC π lter section will be used between the power supply source
and these device pins as shown in Figure 17. The corner frequency of the LC lter is chosen based on the power
supply switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitor C1 is a large electrolytic capacitor to provide the basic cut-off frequency of the LC lter. For example, the
cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitors C2 and C3
are smaller ceramic capacitors designed to provide a low-impedance path for a wide range of high-frequency sig-
nals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the
device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended lter for
the HSI macro is shown below: L= 4.7 H, RL = 1, C1 = 4.7 F, C2 = 0.01 F, C3 = 0.01 F.
Figure 17. Sample Power Supply Filter Network for Analog LI Power Supply Pins
C2
+
C3
+
TO DEVICE
VDDA_[7:4]
VSSA_[7:4]
C1
+
FROM POWER
SUPPLY SOURCE
L
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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