参数资料
型号: ORLI10G1BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 28/78页
文件大小: 1689K
代理商: ORLI10G1BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
34
Embedded Core LVDS I/O
Table 6. Driver dc Data*
*
Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C.
External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%
.
Table 7. Driver ac Data*
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C..
Table 8. Driver Power Consumption*
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage High, VOA or VOB
VOH
RLOAD = 100
1.475
V
Output Voltage Low, VOA or VOB
VOL
RLOAD = 100
0.925
V
Output Differential Voltage
|VOD|
RLOAD = 100
0.25
0.45
V
Output Offset Voltage
VOS
RLOAD = 100
1.125*
1.275
V
Output Impedance, Differential
RO
VCM = 1.0 V and 1.4 V
80
100
120
W
RO Mismatch Between A and B
RO
VCM = 1.0 V and 1.4 V
25
mV
Change in Differential Voltage
Between Complementary States
| VOD|
RLOAD = 100
25
mV
Change in Output Offset Voltage
Between Complementary States
VOS
RLOAD = 100
25
mV
Output Current
ISA, ISB
Driver shorted to GND
24
mA
Output Current
ISAB
Drivers shorted together
12
mA
Power-off Output Leakage
| lxa, lxb |
VDD = 0V
VPAD, VPADN = 0 V—2.5 V
10
mA
Parameter
Symbol
Test Conditions
Min
Max
Unit
VOD Fall Time, 80% to 20%
tF
ZL = 100 ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
100
210
ps
VOD Rise Time, 20% to 80%
tR
ZL = 100 ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
100
210
ps
Differential Skew:
|tPHLA –tPLHB| or
|tPHLB – tPLHA|
tSKEW1
Any differential pair on package at
50% point of the transition
50
ps
Channel-to-channel Skew:
|tpDIFFm – tpDIFFn|
tSKEW2
Any two signals on package at
0 V differential
ps
Propagation Delay Time
tPLH
tPHL
ZL = 100 ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
0.54
0.55
1.10
1.09
ns
Parameter
Symbol
Test Conditions
Min
Max
Unit
Driver dc Power
PDdc
ZL = 100 ± 1%
26.0
mW
Driver ac Power
PDac
ZL = 100 ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
64
W/MHz
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