参数资料
型号: ORLI10G1BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 48/78页
文件大小: 1689K
代理商: ORLI10G1BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
52
Pin Information (continued)
This table describes the I/O signal ports on the embedded core portion of the device.
Table 16. FPSC Function Pin Description
Symbol
I/O
Description
Control and Global Pins
PLL_BYPASS
I
3.3 V active-high. Enables the bypass mode for both receive and both transmit
PLLs.
PWRDN
I
3.3 V active-high. Power down all LVDS links and both receive and both trans-
mit PLLs.
RESET_RX
I
3.3 V active-high. Resets the receive PLLs and the demultiplexer block.
RESET_TX
I
3.3 V active-high. Resets the transmit PLLs and the multiplexer block.
Receive I/O Pins
RX_DAT_IN_N<15:0>
I
LVDS data input for receive side.
RX_DAT_IN_P<15:0>
I
LVDS data input for receive side.
RX_CLK_IN_N<3:0>
I
LVDS clock inputs for receive side.
RX_CLK_IN_P<3:0>
I
LVDS clock inputs for receive side.
Transmit I/O Pins
TX_DAT_OUT_N<15:0>
O
LVDS data outputs on transmit side.
TX_DAT_OUT_P<15:0>
O
LVDS data outputs on transmit side.
TX_CLK_OUT_N<3:0>
O
LVDS clock outputs on transmit side.
TX_CLK_OUT_P<3:0>
O
LVDS clock outputs on transmit side.
TX_CLK_IN_N
I
LVDS transmit reference clock input.
TX_CLK_IN_P
I
LVDS transmit reference clock input.
LVDS Input Reference Pins
LV_REF10
LVDS reference voltage: 1.0 V ± 3%.
LV_REF14
LVDS reference voltage: 1.4 V ± 3%.
LV_RESHI
LVDS resistor high pin (use 100 to LV_RESLO pin).
LV_RESLO
LVDS resistor low pin (use 100 to LV_RESHI pin).
LVCTAP_[6:1]
LVDS input centertap (use 0.01 F to GRD).
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