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参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 12/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
14
SONET Framing
Each 850 Mbits/s serial link uses a pseudo-SONET protocol. SONET A1/A2 framing is used on the link to detect
the 8 kHz frame location. The link is also scrambled using the standard SONET scrambler denition to ensure
proper transitions on the link for improved CDR performance. The ORT8850 can do SONET framing and scram-
bling in both STS-12 and STS-3 formats.
Elastic buffers (FIFOs) are used to align each incoming STS-12 link to the local 77.76 MHz clock and 8 kHz frame.
These FIFOs will absorb delay variations between the eight channels due to timing skews between cards and
along backplane traces. For greater variations, a streamlined pointer processor (pointer mover) within the STM
macro will align the 8 kHz frames regardless of their incoming frame position.
The data rates for SONET are covered in the following table. Values that fall in between those shown in the table for
each mode are supported (126.00 Mbits/s - 212.50 Mbits/s, 504.00 Mbits/s - 850.00 Mbits/s). 63.00 MHz is the
slowest reference clock while 106.25 MHz is the fastest reference clock frequency supported.
Table 2. Supported SONET Data Rates
An STS-N frame can be broadly divided into the Transport Overhead (TOH) and the Synchronous Payload Enve-
lope (SPE) areas. The TOH comprises of bytes that are used for framing, error detection and various other func-
tions. The start of the SPE can begin at any point in a SONET frame. The start of the SPE is determined using the
pointer bytes located in the TOH. The basic STS-1 frame is shown in Figure 4. Higher rate STS_N signals are cre-
ated by byte interleaving N STS-1 signals. Some TOH bytes have slightly different functions in STS-N frames than
in the basic STS-1 frame. The ORT8850 offers both a transparent option and a serial insertion option for process-
ing the TOH bytes.
Figure 4. STS-1 Frame Format
Reference
Clock
STS-12 Mode
STS-3 Mode
63 MHz
504.00 Mbits/s
126.00 Mbits/s
77.76 MHz
622.08 Mbits/s
155.52 Mbits/s
106.25 MHz
850.00 Mbits/s
212.50 Mbits/s
Synchronous
Transport
Overhead
(TOH)
Payload Envelope
(SPE)
3 columns
90 columns
9 rows
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| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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