- 您现在的位置：买卖IC网 > PDF目录1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF资料下载
参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 51/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Lattice Semiconductor
ORCA ORT8850 Data Sheet
5
New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be congured as:
– One—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
– One—256 x 36 (dual-port, one read/one write).
– One—1K x 9 (dual-port, one read/one write).
– Two—512 x 9 (dual-port, one read/one write for each).
– Two RAM with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included
are built-in system registers that act as the control and status center for the device.
Built-in testability:
– Full boundary scan (
IEEE 1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to
IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
Cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route. This
feature also supports compliance with many setup/hold and clock to out I/O specications and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
Programmable Logic System Features
PCI local bus compliant for FPGA I/Os.
Improved
PowerPC/Power QUICC MPC860 and PowerPC II MPC8260 high-speed synchronous MicroProcessor
Interface can be used for conguration, readback, device control, and device status, as well as for a general-pur-
pose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to syn-
chronous
PowerPC processors with user-congurable address space provided.
New embedded
AMBA specication 2.0 AHB system bus (ARM
processor) facilitates communication among
the MicroProcessor Interface, conguration logic, embedded block RAM, FPGA logic, and backplane transceiver
logic.
New network PLLs meet ITU-T G.811 specications and provide clock conditioning for DS-1/E-1 and STS-
3/STM-1 applications.
Variable size bused readback of conguration data capability with the built-in MicroProcessor Interface and sys-
tem bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew (<200
ps for OR4E04).
New local clock routing structures allow creation of localized clock trees.
Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-
speed memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
相关PDF资料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
发布紧急采购，3分钟左右您将得到回复。