参数资料
型号: ORT8850L-3BM680C
厂商: Lattice Semiconductor Corporation
文件页数: 65/105页
文件大小: 0K
描述: IC FPSC TRANSCEIVER 8CH 680-BGA
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 24
系列: *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
62
30017
[0]
R/W
BD resync
0
Channel BD alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[1]
R/W
BC resync
0
Channel BC alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[2]
R/W
BB resync
0
Channel BB alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[3]
R/W
BA resync
0
Channel BA alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[4]
R/W
AD resync
0
Channel AD alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[5]
R/W
AC resync
0
Channel AC alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[6]
R/W
AB resync
0
Channel AB alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[7]
R/W
AA resync
0
Channel AA alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
30018
[0]
R/W
AD/BD resync
0
2-link AD/BD alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[1]
R/W
AC/BC resync
0
2-link AC/BC alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[2]
R/W
AB/BB resync
0
2-link AB/BB alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[3]
R/W
AA/BA resync
0
2-link AA/BA alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[4]
R/W
STM B resync
0
Quad B alignment resync. Write “0” for normal operation.
[5]
R/W
STM A resync
0
Quad A alignment FIFO resync
Write “0” for normal operation.
[6]
R/W
All 8 resync
0
All 8 channel alignment FIFO resync.
Write “0” for normal operation.
[7]
-
Not Used
N/A
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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