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参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 17/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
19
data. When valid SPE data is carried in this H3 slot, SPE is high in this particular TOH time slot also. In the SPE
region, if there is no valid data during any SPE column, the SPE signal will be set to low.
After the pointer interpreter comes the pointer mover block. There is a separate pointer mover for each of the two
SONET quads, A and B, each of which handles up to one STS-48 (four channels) The K1/K2 bytes and H1-SS bits
are also passed through to the pointer generator so that the FPGA can receive them. The pointer mover handles
both concatenations inside the STS-12, and to other STS-12s inside the core. The pointer mover block can cor-
rectly process any length of concatenation of STS frames (multiple of three) as long as it begins on an STS-3
boundary (i.e., STS-1 number one, four, seven, ten, etc.) and is contained within the smaller of STS-3, 12, or 48.
The pointer generator block then maps the corresponding bytes into their appropriate location in the outgoing byte
stream. The generator also creates offset pointers based on the location of the J1 byte as indicated by the pointer
interpreter.
HSI Macrocell - Overview
The HSI macrocell consists of three functionally independent blocks: receiver, transmitter, and PLL synthesizer.
The HSI logic is used for Clock/Data Recovery (CDR) and to serialize and deserialize between the 106.25 MHz
byte-wide internal data buses and the 850 Mbits/s serial LVDS links. For a 622 Mbits/s SONET stream, the HSI will
perform Clock and Data Recovery (CDR) and MUX/DEMUX between 77.76 MHz byte-wide internal data buses
and 622 Mbits/s serial LVDS links.The transmitter block receives parallel data at its input. The MUX (serializer)
module performs a parallel-to-serial conversion using a clock provided by the PLL/synthesizer block. The resulting
serial data stream is then transmitted through the LVDS driver.
The receiver block receives a LVDS serial data without clock at its input. Based on data transitions, the receiver
selects an appropriate clock phase for each channel to retime the data. The retimed data and clock are then
passed to the DEMUX (deserializer) module. The DEMUX module performs serial-to-parallel conversion and pro-
vides parallel data and clock to the SONET framer block.
Supervisory and Test Support Features - Overview
The supervisory and test support functions provided by the ORT8850 include data integrity monitoring, error inser-
tion capabilities and loopback support. These functions are described in the following sections.
Integrity Monitoring
FPGA Parallel Bus Integrity: Parity error checking is implemented on each of the four parallel input buses on each
STM quad (A & B). "Even" or "Odd" parity can be selected by setting a control register bit. Upon detection of an
error, an alarm bit is set. This feature is on a per channel basis. Note that, on parallel output ports, parity is calcu-
lated over the 8-bit data bus and not on the SPE and C1J1 lines.
TOH Serial Port Integrity: There is “even” parity generation on each of the four TOH serial output ports. There is
“even” parity error checking on each of the four TOH serial input ports. There is one parity bit embedded in the TOH
frame. It occupies the Most Signicant Bit location of A1 byte of STS#1. Upon detection of an error, an alarm bit is
set. This feature is on a per channel basis.LVDS Link Integrity: There is B1 parity generation on each of the four
LVDS output channels. There is also performance monitoring on each of the four LVDS input channels, imple-
mented as B1 parity error checking. Upon detection of an error, a counter is incremented (one count per errored
bit) and an alarm bit is set. The counter is 7-bits wide plus 1 overow indicator bit. This feature is on a per channel
basis.
Framer Monitor: The framer in the receive direction will report Loss of Frame by setting an alarm bit, as well as a
LOF count and errored frame count. The LOF alarm bit is not clearable as long as the channel is in the LOF state.
In addition, the errored frame count represents errored frames, and will not increment more than once per frame
even if there are multiple errors.
Receiver Internal Path Integrity: There is "even" parity generation in the Receiver section (after descrambler). There
is also "even" parity error checking in the Receiver section (before output). Upon detection of an error, an alarm bit
is set. This feature is on a per channel basis.
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相关代理商/技术参数 |
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| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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