Lattice Semiconductor
ORCA ORT8850 Data Sheet
21
Figure 8. Data Paths for Near-End and Far-End Loopbacks (Single Channel)
Near end loopback is a loopback of data from the FPGA transmit into the core and back out of the core to the
FPGA. This loopback mode is good for simulation since two ORT8850 devices do not have to be included in the
simulation test bench. It is also ideal for system debugging when only working with a single card. There are two
depths to the near end loopback, CDR and LVDS. The CDR near end loopback performs the loopback inside the
CDR itself. LVDS near end loopback does the loopback just before data is sent out of the LVDS transmit pins. In all
near end loopbacks the transmit data is still sent out of the LVDS pins.
Far end loopback is a loopback of the high speed data on the backplane side. Serial data is transmitted into the
device from the backplane and then looped back to the backplane side. This loopback is good for backplane con-
nectivity tests and backplane integrity type tests. The actual loopback of data is performed inside the Pointer Mover
Block. In this mode the SYS_FP signal from the FPGA logic to the Embedded Core must provide an 8KHz frame
pulse. It should also be noted that during the bypass of the Pointer Mover Block, the Far End Loopback cannot be
performed inside the Embedded ASIC Block. In that case it can be coded to be performed inside the FPGA.
Protection Switching - Overview
The ORT8850 supports 1:1 redundancy within both the transmit and receive data paths. Work/protect selection is
controlled by a control register bit which can be set using the system bus or the external MicroProcessor Interface.
Protection switching allows a pair of SERDES channels to act as main and protect data links. On the transmit side,
a simple broadcast mode is used and the same data is transmitted across both work and protect interfaces.
All data channels have receive work and protect switching capability. There are two types of receive protection
switching supported. The switching can be performed at the parallel interface to the FPGA or at the interface to the
LVDS buffers. Parallel protection switching
(Figure 9) takes place just before the FPGA interface ports and after the
alignment FIFO. The alignment FIFO must be used for this type of protection switching. In this mode SERDES
channels AA and AB are used as main and protect. When selected for main channel AA is used to provide data on
FPGA interface ports AA. When selected for protect channel AB is used to provide data on FPGA interface ports
Parallel
Loopback
Connection
Test Equipment or
Remote System
Card
(a) “ Near End ” Loopback
Embedded Core
2
FPGA Logic
m
n
Data
Checking
Data
Generation
Non-Functional
Active
(to Eye Diagram
Measurement or
Remote System
Card)
Receive
Transmit
ORT8850 Device Under Test (DUT)
LVDS
Buffer
LVDS
Buffer
High Speed
Serial Loopback
Connection
32
Test Equipment
or Logic on Local
System Card
TXDxx_[W:P]_[ P:N]
RXDxx_[W:P]_[P:N]
(b) “ Far End ” Loopback
SERDES
And
LVDS
Buffers
Embedded Core
FPGA Logic
m
n
Non-Functional
Receive
Transmit
ORT8850 Device Under Test (DUT)
2
Data
Checking
Data
Generation
RX SONET
TX SONET
TXDxx_[W:P]_[ P:N]
Note: xx = AA, ..., BD
RXDxx_[W:P]_[P:N]
Active
(to Logic on
Local System
Card)