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| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 73/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
7
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a congured FPGA. This system
is used to map a design onto the
ORCA architecture and then place and route it using ispLEVER's timing-driven
tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design
entry, synthesis, simulation, and timing analysis.
The ispLEVER development system interfaces to front-end design entry tools and provides the tools to produce a
congured FPGA. In the design ow, the user denes the functionality of the FPGA at two points in the design ow,
the design entry and the bit stream generation stage. Recent improvements in ispLEVER allow the user to provide
timing requirement information through logical preferences only; thus, the designer is not required to have physical
knowledge of the implementation.
Following design entry, the development system's map, place, and route tools translate the netlist into a routed
FPGA. A oor planner is available for layout feedback and control. A static timing analysis tool is provided to deter-
mine design speed, and a back-annotated netlist can be created to allow simulation and timing.
Timing and simulation output les from ispLEVER are also compatible with many third-party analysis tools. A bit
stream generator is then used to generate the conguration data which is loaded into the FPGAs internal congu-
ration RAM, embedded block RAM, and/or FPSC memory.
When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined
with the front-end tools, ispLEVER produces conguration data that implements the various logic and routing
options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER software and third-party synthesis
and simulation engines, provides all software and documentation required to design and verify an FPSC implemen-
tation. Included in the kit are the FPSC conguration manager,
Synopsys Smart Model
, and/or compiled Verilog
simulation model,
HSPICE
and/or IBIS models for I/O buffers, and complete online documentation. The kit's soft-
ware couples with ispLEVER software, providing a seamless FPSC design environment. More information can be
obtained by visiting the Lattice website at www.latticesemi.com or contacting a local sales ofce.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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