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| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 37/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
37
passes, the next state will either still be Frame Conrm or will be In Frame. For the framer to declare an In Frame
state the framer must detect 4 consecutive correct A1/A2 framing patterns.
This state is similar to the Frame Conrm state except that if the comparison at the A1/A2 time is incorrect, the next
state will be the Errored Frame state. If the comparison is correct, the next state will be In Frame. Data is only valid
in the Frame state
Errored Frame State
Once the Errored Frame state has been reached, if the next comparison is incorrect, the next state will be OOF i.e.,
after two transitions are missed, the state machine goes into the OOF state which will also generate an alarm. Oth-
erwise, if the comparison correct, the next state will be In Frame. Also, when the framer detects an errored frame it
increments an A1/A2 frame error counter register accessible from the system bus. The counter can be monitored
by a processor to compile performance status on the quality of the backplane.
B1 Parity Error Check
The B1 parity error check block receives byte-wide scrambled byte-wide parallel data and a frame sync from the
framer. The B1 error check calculation block computes a BIP-8 (bit interleaved parity 8 bits) code, using even parity
over all bits of the current STS-12 frame before descrambling.
The same calculation had previous been done for the previous STS-12 frame. The value obtained then is checked
against the B1 byte of the current frame after descrambling. A per-stream B1 error counter is incremented for each
bit that is in error. The error counter register is accessible from the system bus.
Descrambler
The received streams from the framer are descrambled using a frame synchronous descrambler with the same
polynomial (1 + x
6 + x7) that was used in the transmit path. If the incoming data is not scrambled, the descrambling
function can be disabled by setting a control register bit (0x3000C). The A1/A2 framing bytes, the section trace byte
(C1/J0) and the growth bytes (Z0) are not descrambled.
AIS-L Insertion
The Alarm Indication Signal (AIS) is a continuous stream of unframed 1s sent to alert downstream equipment that
the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. AIS-L is
inserted into the received frame by writing all ones for all bytes of the descrambled stream under two conditions:
1.
If a force AIS_L state is enabled by a bit in the AIS-L force register, AIS-L is inserted into the received frame
continuously. This will cause all bytes within a STS-12 frame to be FF
2.
If an AIS-L Insertion on Out-Of-Frame enabled via a register, AIS-L is inserted into the received frame when
the framer indicates that an out-of-frame condition exists.
Since this occurs after the overhead processing block, all Transport Overhead can continue to byte read and B1
can still be used to monitor link integrity.
Alignment FIFO and Multi-Channel Alignment
The alignment FIFO in the ORT8850 performs two functions, clock domain transfer and multi-channel alignment.
The depth of the alignment FIFO is 10 bit words which allows it to absorb channel timing differences of up to 18
clock cycles. Multi-channel alignment is based on the incoming A1/A2 bytes.
The alignment FIFO is always written from the SONET framer using the per channel recovered clock. The FIFO is
always read using the local reference clock (FPGA_SYSCLK). For this reason when doing multi-channel alignment
there must be 0 ppm between the transmit ORT8850 reference clock and the receiving ORT8850 reference clock.
This can only be accomplished by using a single clock source for both the transmitting and receiving devices.
The alignment FIFO has several alarm and control indicators that are accessible via control and alarm registers
available via the system bus or the MPI. The default alignment threshold values for the alignment FIFO are set in
registers at 0x3000A and 0x3000B. Here the min and max threshold values can be programmed. The default min is
set to 2 clocks and the max default is set to 15. If the alignment FIFO determines that these thresholds have been
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| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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