Lattice Semiconductor
ORCA ORT8850 Data Sheet
65
30027*
0303F
30057
3006F
30087
3009F
300B7
300CF
[0]
R/W
enable channel
alarm
0
Channel alarm bit (30026, ...) enable. Set to 1 to enable
alarm bit to propagate to alarm 0x30010
[1]
R/W
enable AIS-P ag
0
AIS -P ag alarm enable. Set to 1 to enable alarm bit to
propagate to alarm 0x30010
[2]
enable pointer
mover elastic
store overow
ag
0
Pointer mover elastic store overow ag enable. Set to 1 to
enable alarm bit to propagate to 0x30010
[3-7]
-
Not Used
0
30028*
30040
30058
30070
30088
300A0
300B8
300D0
[0]
R
FIFO aligner
threshold error
ag
00
Alarm is set to 1 if either the min or max FIFO threshold
levels are violated, the min and max threshold levels can
be set in address 0x3000A and 0x300B. Alarm enable is
0x30029 bit 0. Write 1 to clear this alarm bit This alarm is
only valid when FIFO OOS ag is also set.
[1]
RX internal path
parity error ag
Alarm indicator on receive path internal parity error. Alarm
is enabled in 0x30029 bit 1. Write 1 to clear
[2]
OOF ag
Alarm indicator channel is OOF. Alarm enable is 0x30029
bit 2. Write 1 to clear.
[3]
LVDS link B1 par-
ity error ag
Alarm indicator that channel has found a B1 parity error.
Alarm enable is 0x30029 bit 3. Write 1 to clear.
[4]
DINxx parallel
bus parity error
ag
0
Alarm indicator channel has found a parity error on the
DINxx input from the FPGA.Alarm enable is 0x30029 bit 4.
Write 1 to clear.
[5]
TOH serial input
port parity error
ag
0
Alarm indicator channel has found a parity error on the
TOH_INxx input from the FPGA. Write 1 to clear this
alarm. Alarm enable is 0x30028 bit 5.
[6]
FIFO OOS error
ag
0
Alarm indicates channel group is out of sync. Write 1 to
clear. Alarm enable is 0x30028.
[7]
-
Not Used
0
30029*
30041
30059
30071
30089
300A1
300B9
300D1
[0:6]
R/W
channel alarm
enable
00
Enable bits for channel alarm register 0x30028. Set to 1 to
enable and to propagate the alarm to register 0x30026 bit
0.
[7]
-
Not Used
0
3002A*
30042
3005A
30072
3008A
300A2
300BA
300D2
[0:3]
R
AIS alarm ags 3,
6, 9, 12
0
These are the AIS-P alarm ags. 1 if the LVDS input STS #
contains AIS.
[4-7]
-
Not Used
0
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description