- 您现在的位置：买卖IC网 > PDF目录1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF资料下载
参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 50/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Lattice Semiconductor
ORCA ORT8850 Data Sheet
49
Clock and Data Timing at the FPGA/Embedded Core Interface - SONET Block
(Note: This section assumes a basic understanding of the Lattice Semiconductor ispLEVER design tool set)
This section provides examples of the clock and data timing relationships at the FPGA/Embedded Core interface
for both the parallel SONET data and the serial TOH data. The initiation of a change of data is referred to as the
"launch" time and the actual time of capture of the data is referred to as the "capture" time. Two relationships are
discussed, the relationship between data and clock at the interface itself and the relative timing constraints on the
signals in the FPGA logic between the interface and the launch/capture latch in the FPGA portion of the FPSC.
The ispLEVER place and route tool will automatically attempt to meet the timing constraints by placing a frequency
constraint on the corresponding clock and will report a non-routed condition if it is unable to do so. Trace reports
should also be generated using ispLEVER to evaluate both the setup and the hold margins.
The typical timing numbers used in the discussions are for illustration purposes and can vary due to both process
and environmental variations and to differences in the routing through the FPGA logic, especially for the data path.
Exact timing numbers should always be obtained from ispLEVER.
In all of the discussions in this section, the maximum reference clock frequency of 106 MHz is assumed. The pri-
mary clock path delay was assumed to be 3 ns - this delay is well controlled in the FPGA logic. A secondary clock
path delay can vary from 1 to 3.5 ns - a delay of 2.5 ns was used in the payload data discussions and 2 ns for the
TOH discussions.
The ve cases considered in the discussion are shown in Table 16. The clock routing and timing congurations
shown in this section are recommended for the general user since they give the best timing margins. In the discus-
sion, if both the core and FPGA launch and latch data on the same edge, it is referred to as a "full cycle" mode. If
they launch and latch on different edges, it is referred to as a "half cycle" mode.
TOH_xx_EN
O
Indicates state of register settings for TOHxx_EN
PROT_SWITCH_AA
I
Parallel protection switch select, Channels AA and AB
PROT_SWITCH_AC
I
Parallel protection switch select, Channels AC and AD
PROT_SWITCH_BA
I
Parallel protection switch select, Channels BA and BB
PROT_SWITCH_BC
I
Parallel protection switch select, Channels BC and BD
LVDS_PROT_AA
I
LVDS protection switch select, Channel AA
LVSD_PROT_AB
I
LVDS protection switch select, Channel AB
LVDS_PROT_AC
I
LVDS protection switch select, Channel AC
LVDS_PROT_AD
I
LVDS protection switch select, Channel AD
LVDS_PROT_BA
I
LVDS protection switch select, Channel BA
LVDS_PROT_BB
I
LVDS protection switch select, Channel BB
LVDS_PROT_BC
I
LVDS protection switch select, Channel BC
LVDS_PROT_BD
I
LVDS protection switch select, Channel BD
Table 15. FPGA/Embedded Core Interface Signals (Continued)
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
FPGA/Embedded Core
Interface Signal Name
xx=[AA,…,BD]
Input (I) to or Output (O)
from Core
Signal Description
相关PDF资料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
发布紧急采购，3分钟左右您将得到回复。