- 您现在的位置：买卖IC网 > PDF目录1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF资料下载
参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 22/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Lattice Semiconductor
ORCA ORT8850 Data Sheet
23
reset and all the local bus interface signals forced high, but the following active-high signals, PROT_SWITCH_AA,
PROT_SWITCH_AC, PROT_SWITCH_BA, PROT_SWITCH_BC, TX_TOH_CK_EN, SYS_FP, LINE_FP, will be
forced low. The CORE_READY signal sent from the embedded core to FPGA is held low, indicating that the core is
not ready to interact with FPGA logic. At the end of the FPGA conguration sequence, the CORE_READY signal
will be held low for six SYS_CLK cycles after DONE, TRI_IO and RST_N (core global reset) are high. Then it will go
active-high, indicating the embedded core is ready to function and interact with FPGA programmable circuit. During
FPGA reconguration when DONE and TRI_IO are low, the CORE_READY signal sent from the core to FPGA will
be held low again to indicate the embedded core is not ready to interact with FPGA logic. During FPGA partial con-
guration, CORE_READY stays active. The same FPGA conguration sequence described previously will repeat
again.
The initialization of the embedded core consists of two steps: register conguration and synchronization of the
alignment FIFO. The steps to congure the ORT8850 device for normal operation are listed in Table 4 and Table 5.
Generic Backplane Transceiver Application
Independent Channels, Transparent TOH: Table 4 lists the register values to setup the ORT8850 as eight inde-
pendent SONET channels (no alignment) using transparent TOH. The order is specic. The values are given from
the PowerPC point of view. If using the MPI to write data to the ORT8850, the value given in the table is the value
that should be used. If using the UMI of the system bus, the data value would need to be byte ipped.
Table 4. Independent Channels, Transparent TOH
Register
Address
Value
Description
0x30004
0x05
Lock register. This value must be written to allow writing to any other ORT8850 core register
0x30005
0x80
Lock register. This value must be written to allow writing to any other ORT8850 core register
0x30020
0x07
Turn on Channel AA in functional mode
0x30021
0xFF
Channel AA - Transparent TOH from parallel data
0x30022
0xFF
Channel AA - Transparent TOH from parallel data
0x30038
0x07
Turn on Channel AB in functional mode
0x30030
0xFF
Channel AB - Transparent TOH from parallel data
0x3003A
0xFF
Channel AB - Transparent TOH from parallel data
0x30050
0x07
Turn on Channel AC function mode
0x30051
0xFF
Channel AC - Transparent TOH from parallel data
0x30052
0xFF
Channel AB - Transparent TOH from parallel data
0x30068
0x07
Turn on Channel AD in functional mode
0x30069
0xFF
Channel AD - Transparent TOH from parallel data
0x3006A
0xFF
Channel AD - Transparent TOH from parallel data
0x30080
0x07
Turn on Channel BA functional mode
0x30081
0xFF
Channel BA- Transparent TOH from parallel data
0x30082
0xFF
Channel AD - Transparent TOH from parallel data
0x30098
0x07
Turn on Channel BB in functional mode
0x30099
0xFF
Channel BB- Transparent TOH from parallel data
0x3009A
0xFF
Channel BB- Transparent TOH from parallel data
0x300B0
0x07
Turn on Channel BC in functional mode
0x300B1
0xFF
Channel BC- Transparent TOH from parallel data
0x300B2
0xFF
Channel BC - Transparent TOH from parallel data
0x300C8
0x07
Turn on Channel BD in functional mode
0x300C9
0xFF
Channel BD - Transparent TOH from parallel data
0x300CA
0xFF
Channel BD - Transparent TOH from parallel data
相关PDF资料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
发布紧急采购，3分钟左右您将得到回复。