- 您现在的位置：买卖IC网 > PDF目录1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF资料下载
参数资料
| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 58/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页当前第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Lattice Semiconductor
ORCA ORT8850 Data Sheet
56
Powerdown Mode
Powerdown mode will be entered when the corresponding channel is disabled. Channels can be independently
enabled or disabled under software control.
Parallel data bus output enable and TOH serial data output enable signals are made available to the FPGA logic.
The HSI macrocell’s corresponding channel is also powered down. The device will power up with all eight channels
in powerdown mode.
Protection Switching
There is built-in protection switching between the SERDES channels, in the receive direction of the ORT8850. Pro-
tection switching allows pairs of SERDES channels to act as main and protect data links, and to switch between the
main and protect links via a control register or FPGA interface port. There are two types of protection switches: par-
allel and LVDS.
Parallel protection switching takes place just before the FPGA interface ports, and after the alignment FIFO. The
alignment FIFO must be used for this type of protection switching. It is possible to bypass the pointer inter-
preter/mover and still use the parallel protection switching. In this mode, SERDES channels AA and AB are used
as main and protect. When selected for main, channel AA is used to provide data on interface ports AA. When
selected for protect, channel AB is used to provide data on FPGA interface ports AA. The same scheme is used for
channel groupings AC/AD, BA/BB, and BC/BD
There are two ways to control the parallel protection switching, interface signal and software control. On the FPGA
interface, there are 4 input signals to the ORT8850 core that will select between a main and a protect channel.
When using the interface signal to control protection switching, only the parallel data is switched; the serial TOH
data outputs are not switched.
Software control will switch both the parallel data and the serial TOH data outputs to the FPGA. The software con-
trol register is found at 0x30009 in the memory map (Table 19).
Table 17. Register Settings, Parallel Protection Switching
LVDS protection switching takes place at the LVDS buffer before the serial data is sent into the Data Recovery
(CDR). The selection is between the main LVDS buffer and the protect LVDS buffer. The work LVDS buffers are
TXDxx_W_[P:N], while the protect LVDS buffers are TXDxx_P_[P:N]. When operating using the LVDS buffers
(default), no status information is available on the protect LVDS buffers since the serial stream must reach the
SONET framer before status information is available on the data stream. The same is also true for the work LVDS
buffers when operating with the protect buffers.
There are two ways to control the LVDS protection switching, interface and software control. On the FPGA inter-
face, there are eight input signals to the ORT8850 core that will select between the work and protect LVDS buffers.
FPGA Interface Signal
When ‘0’
When ‘1’
PROT_SWITCH_AA
Channel AB data on DOUTAA
Channel AA data on DOUTAA
PROT_SWITCH_AC
Channel AD data on DOUTAC
Channel AC data on DOUTAC
PROT_SWITCH_BA
Channel BB data on DOUTBA
Channel BA data on DOUTBA
PROT_SWITCH_BC
Channel BD data on DOUTBC
Channel BC data on DOUTBC
Table 18. LVDS Protection Switching
FPGA Interface Signal
When ‘0’
When ‘1’
LVDS_PROT_AA
Channel AA gets TXD_AA_W_[P:N]
Channel AA gets TXD_AA_P_[P:N]
LVDS_PROT_AB
Channel AB gets TXD_AB_W_[P:N]
Channel AB gets TXD_AB_P_[P:N]
LVDS_PROT_AC
Channel AC gets TXD_AC_W_[P:N]
Channel AC gets TXD_AC_P_[P:N]
LVDS_PROT_AD
Channel AD gets TXD_AD_W_[P:N]
Channel AD gets TXD_AD_P_[P:N]
相关PDF资料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
发布紧急采购，3分钟左右您将得到回复。