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参数资料
型号： ORT8850L-3BM680C
厂商： Lattice Semiconductor Corporation
文件页数： 86/105页
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
81
Package Information
Table 34 summarizes the programmable I/O clock and power pins available to the ORT8850 devices.
Table 34. ORT8850 IO and Power Pin Summary
There are some incompatibilities between the ORT8850H and ORT8850L due to the fact that the ORT8850L is a
much smaller array and hence does not provide as many programmable IOs (PIOs). In order to allow pin-for-pin
compatible board layouts that can accommodate either device, key compatibility issues include the following:
Unused Pins Table 35 shows a list of bonded ORT8850H PIOs that are unused in the ORT8850L. As shown in
the table, there are 19 balls that are not available in the ORT8850L, but are available in the ORT8850H. These
user I/Os should not be used if an ORT8850L will be used.
Shared Control Signals on I/O Registers. The ORCA Series 4 architecture shares clock and control signals
between two adjacent I/O pads. If I/O registers are used, incompatibilities may arise between ORT8850L and
ORT8850H when different clock or control signals are needed on adjacent package pins. This is because one
device may allow independent clock or control signals on these adjacent pins, while the other may force them to
be the same. There are two ways to avoid this issue.
– Always keep an open bonded pin (non-bonded pins for the ORT8850L do not count) between pins that
require different clock or control signals. Note that this open pin can be used to connect signals that do not
require the use of I/O registers to meet timing.
– Place and route the design in both the ORT8850H and ORT8850L to verify both produce valid designs. Note
that this method guarantees the current design, but does not necessarily guard against issues that can
occur when design changes are made that affect I/O registers.
– 2X/4X I/O Shift Registers. If 2X I/O shift registers or 4X I/O shift registers are used in the design, this may
cause incompatibilities between the ORT880L and ORT8850H because only the A and C I/Os in a PIC sup-
port 2X I/O shift registers and only A I/Os supports 4X I/O shift register mode. A and C I/Os are shown in the
following pinout tables under the I/O pad columns as those ending in A or C.
Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are
shown in the following pinout tables under the I/O pad columns as those ending in C.
I/O or Power Type
ORT8850L
ORT8850H
User I/O Single Ended
278
297
User I/O Differential Pairs (LVDS, LVPECL)
129
Conguration
7
Dedicated Function
3
VDD15
48
VDD33
28
VDDIO
38
Vss
89
Single-Ended/Differential I/O per Bank
Bank 0
64/32
68/32
Bank 1
47/20
Bank 2
ASIC I/O
Bank 3
ASIC I/O
Bank 4
ASIC I/O
Bank 5
44/18
Bank 6
76/32
Bank 7
55/27
62/27
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