参数资料
型号: ORT8850L-3BM680C
厂商: Lattice Semiconductor Corporation
文件页数: 61/105页
文件大小: 0K
描述: IC FPSC TRANSCEIVER 8CH 680-BGA
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 24
系列: *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
59
30009
[0]
R/W
TOH serial port
output MUX select
for AA/AB
1
0 = AB TOH is output on AA
1 = AA TOH is output on AA
[1]
R/W
TOH serial port
output MUX select
AC/AD
1
0 = AD TOH is output on AC
1 = AC TOH is output on AC
[2]
R/W
DOUT parallel port
output MUX select
for AA/AB
1
0 = AB data is output on AA
1 = AA data is output on AA
[3]
R/W
DOUT parallel port
output MUX select
for AC/AD
1
0 = AD data is output on AC
1 = AC data is output on AC
[4]
R/W
TOH serial port
output MUX select
for BA/BB
1
0 = BB TOH is output on BA
1 = BA TOH is output on BA
[5]
R/W
TOH serial port
output MUX select
for BC/BD
1
0 = BD TOH is output on BC
1 = BC TOH is output on BC
[6]
R/W
DOUT parallel port
output MUX select
for BA/BB
1
0 = BB data is output on BA
1 = BA data is output on BA
[7]
R/W
DOUT parallel port
output MUX select
BC/BD
1
0 = BD data is output on BC
1 = BC data is output on BC
3000A
[0:4]
R/W
FIFO aligner
threshold value
(min)
40
decimal
2
Minimum threshold value for the per channel receive direction
alignment FIFOs. If and when the minimum threshold value is
violated by a particular channel, then the “FIFO aligner thresh-
old error” alarm bit will be generated for that channel and if
enabled, latched as a “FIFO aligner threshold error ag” in the
respective channel alarm register.
The allowable range for minimum threshold values is 1 to 23.
Note that the minimum FIFO aligner threshold value applies to
all eight channels.
MSB bit is 4.
[5-7]
-
Not Used
N/A
3000B
[0:4]
-
FIFO aligner
threshold value
(max)
A8
decimal
15
The allowable range for maximum threshold values is 0 to 22.
MSB bit is 4
[5-7]
-
Not Used
N/A
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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