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| 型号： | ORT8850L-3BM680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 42/105页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
41
to all eight channels. All TOH bytes from the STS-12 streams are transferred over the appropriate serial link in the
same order in which they appear in a standard STS-12 frame.
During the SPE time, the receiver TOH frame pulse is generated (RX_TOH_FP) which indicates the start of the row
of 36 TOH bytes. This pulse, along with the receive TOH clock enable (RX_TOH_CK_EN), as well as the TOH data,
are all launched on the rising edge of the TOH clock (TOH_CLK).
On the TOH serial port, all TOH bytes are sent as received on the LVDS input (MSB rst). The only exception is the
most signicant bit of byte A1 of STS#1, which is replaced with an even parity bit. This parity bit is calculated over
the previous TOH frame. Also, on AIS-L (either resulting from OOF or forced through software), all TOH bits are
forced to all ones with proper parity (parity automatically ends up being set to 1 on AIS-L).
The Core logic must provide framing information to the FPGA using the RX_TOH_CK_EN and RX_TOH_FP output
signals. TOH data is output on a row by row basis, with the one clock cycle frame pulse (RX_TOH_FP) delineating
the start of a row, as shown in Figure 21. Detailed timing for the TOH serial output is shown in later in Figure 29.
Figure 21. TOH Serial Port Output Framing Signals (Core to FPGA)
Receiver TOH reconstruction on the output parallel bus is performed as shown in the following table (if the pointer
mover is not bypassed).
Table 12. Receiver TOH Byte Reconstruction (Output Parallel Bus)
Special TOH Byte Functions
The K1 and K2 bytes are used in Automatic Protection Switch (APS) applications. K1 and K2 bytes can be option-
ally passed through the pointer mover under software control, or can be set to zero with the other TOH bytes.
A1
A2
0
H1
H2
H3
0
K2
0
K2
0
Regenerated bytes.
Regenerated bytes (under pointer control. SS bits must be transparent, AIS-P must be supported)
Bytes taken from elastic store buffer on negative stuff opportunity - else forced to all zeroes
Transparent or all zeros (K1/K12 are either taken from K1/K12 buffer or forced to all zero-soft control) In transport mode, AIS-L must be supported.
All zero bytes
DOUTxx[7:0]
36 bytes TOH
1044 bytes SPE
Row 1
TOH_CLK
RX_TOH_FP
RX_TOH_CK_EN
Data Valid
TOH_OUTxx
bit 6
of A1 byte STS1 #1
MSbit(7)
of A1 byte STS1 #1
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相关代理商/技术参数 |
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| ORT8850L-3BMN680C | 功能描述:FPGA - 现场可编程门阵列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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