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参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 18/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
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Datasheet
25
Pentium III Processor for the PGA370 Socket up to 750 MHz
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT. These termination resistors are placed electrically between the ends of the signal
traces and the VTT voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called VREF. Refer to the appropriate platform design guide for more information
Table 9 below lists the nominal specification for the AGTL+ termination voltage (VTT). The
AGTL+ reference voltage (VREF) is generated on the system motherboard and should be set to 2/3
VTT for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the Intel Pentium II Processor Developer's Manual and AP-585,
Intel
Pentium II Processor AGTL+ Guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Pentium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. VTT and Vcc1.5 must be held to 1.5V ±9%. It is required that VTT and Vcc1.5 be held to 1.5V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. See
Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific
chipset/processor combination.
5. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 10 through Table 16 list the AC specifications associated with the processor system bus.
These specifications are broken into the following categories: Table 10 contains the system bus
clock specifications, Table 12 contains the AGTL+ specifications, Table 13 contains the CMOS
signal group specifications, Table 14 contains timings for the reset conditions, Table 15 and covers
APIC bus timing, and Table 16 covers TAP timing.
All processor system bus AC specifications for the AGTL+ signal group are relative to the rising
edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’ logic
levels unless otherwise specified.
Table 9.
Processor AGTL+ Bus Specifications 1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
VTT
Bus Termination Voltage
1.50
V
3
On-die RTT
Termination Resistor
40
130
4
VREF
Bus Reference Voltage
0.950
2/3 VTT
1.05
V
5
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
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